EP0029834A1 - Tampon de donnees a usages multiples - Google Patents

Tampon de donnees a usages multiples

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Publication number
EP0029834A1
EP0029834A1 EP19800900984 EP80900984A EP0029834A1 EP 0029834 A1 EP0029834 A1 EP 0029834A1 EP 19800900984 EP19800900984 EP 19800900984 EP 80900984 A EP80900984 A EP 80900984A EP 0029834 A1 EP0029834 A1 EP 0029834A1
Authority
EP
European Patent Office
Prior art keywords
data
port
signal
output
input
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP19800900984
Other languages
German (de)
English (en)
Inventor
Kenneth George William Ritchie
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Unisys Corp
Original Assignee
Burroughs Corp
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Filing date
Publication date
Application filed by Burroughs Corp filed Critical Burroughs Corp
Publication of EP0029834A1 publication Critical patent/EP0029834A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F7/00—Methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F7/76—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data
    • G06F7/78—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor
    • G06F7/785—Arrangements for rearranging, permuting or selecting data according to predetermined rules, independently of the content of the data for changing the order of data flow, e.g. matrix transposition or LIFO buffers; Overflow or underflow handling therefor having a sequence of storage locations each being individually accessible for both enqueue and dequeue operations, e.g. using a RAM

Definitions

  • the present invention relates to a general purpose data storage device for use, in any selectable one of a plurality of operating modes, for the storage and transfer of data between any selectable two out of a plurality of data ports.
  • a device for storing data and transferring it between any selectable pair out of a plurality of data ports comprising a control port, input selection means operable in response to a first external command applied to said control port to select a first one of said ports as a data input port, output selections means, operable in response to a second external command applied to said control port to select a second one of said ports as a data output port, a memory for retrievably storing a plurality of data characters, writing means, operable in response to a third external command applied to said control port to store in said memory a succession of data characters received at said first port, and reading means, operable in response to a fourth external command applied to said control port to retrieve said characters from said memory and present them, one by one to said second port, in any selectable one out of a plurality of serial orders.
  • a general purpose data buffer employs a control logic circuit for selecting an access mode for a random access memory.
  • the random access memory is coupled to two or more bidirectional data ports through a data input multiplexer and a data output register.
  • the control logic circuit enables the random access memory to function as a first-in/first-out data buffer, a last-in/first-out stack memory, a variable-length shift register or a block-readable or writable random acces memory.
  • the control logic circuit designates which of the data ports is an input port and which of the data ports is an output port.
  • the general purpose data buffer further includes a length register for selecting the number of data characters being transferred at one time as well as read and write address pointers for selecting the locations with the random access memory for data transfer. Data transfer between the I/O ports and the random access memory is synchronized by a single buffer clock.
  • Figure 1 is a system block diagram of the general purpose data buffer.
  • Figure 2 is a logical embodiment of the control logic module of the general purpose data buffer.
  • Figure 3 is a logical embodiment of the random access comparator and random access multiplexer of the general purpose data buffer.
  • Figure 4 is a logical embodiment of the write address pointer register and status logic module of the general purpose data buffer of Figure 1.
  • Figure 5 is a detailed logical implementation of a write address register cell of the write address register of the general purpose data buffer of Figure 1.
  • Figure 6 is a logical embodiment of the masked length selector, the length register, the length multiplexer, and the data input multiplexer of the general purpose data buffer of Figure 1.
  • Figure 7 is a detailed logical embodiment of a data input cell of the data input multiplexer of the general purpose data buffer of Figure 1.
  • Figure 8 is a logical embodiment of the read address pointer register of Figure 1.
  • Figure 9 is a detailed logical embodiment of a read address register cell of the read address pointer register of the general purpose data buffer of Figure 1.
  • Figures 10A and 10B are logical embodiments of the port A logic, port B logic, and output register of the general purpose data buffer of Figure 1.
  • Figure 11A is a detailed logical embodiment of a port
  • FIG. 11B is a detailed logical embodiment of a port B cell employed in the port B logic of the general purpose data buffer of Figure 1.
  • Figure 11C is a detailed logical embodiment of an output register cell employed in the data output register of the general purpose data buffer of Figure 1.
  • Figure 12 is a block diagram of the random access memory of the general purpose data buffer of Figure 1.
  • Figure 1 is a block diagram of the system which comprises the general purpose data buffer.
  • the control logic module 11 receives inputs I ⁇ -I2 which designate the particular accessing mode for the random access memory module.
  • the control logic module 11 also receives a clock signal PH1, an output enable signal (OE), and a designation of which of the data ports coupled to the general purpose data buffer is to be treated as an input port and which is to be treated as an output port. This is labelled the direction signal (DIR).
  • a stack-designation signal is also provided to the control logic module 11 when the random access memory is to be operated in the stack mode. These signals are all provided by some device such as a central processor which is external to the general purpose data buffer.
  • the control logic module is used to generate all control signals within the circuit in accordance with the state of the instruction inputs I ⁇ -I2 and the clock and other input signals.
  • a memory module 13 is a standard random access memory which could comprise
  • Figure 1 also illustrates, data input/output port A with its associated control logic 15 and data input/output port B with its associated control logic 17.
  • data port A and data port B are bidirectional in nature and will normally function in mutually opposite data-flow directions. This means that when port A 15 is the source of information for the random access module 13, then data port B 17 will be the destination of the data which will be supplied from the random access memory module 13.
  • the control logic module 11 is coupled to the write address pointer register 19 and the read address pointer register 21.
  • These registers 19, 21 are 8-bit binary up/down counters with parallel-load facility.
  • the write address pointer register 19 addresses the random access memory (RAM) module 13 when data is to be written into the memory
  • the read address pointer register 21 addresses the RAM when data is being read from the memory. Both registers can be loaded with external data such as an address from either of the I/O ports 15, 17 or with the contents of the programmed length register 33 or the masked length register 37.
  • the write address pointer register 19 and the read address pointer register 21 are both coupled to the RAM address multiplexer 23.
  • the multiplexer 23 selects -either the contents of the write address pointer 19 or the read address pointer 21 as the address for the RAM 13.
  • the RAM address comparator 25 is employed to compare the contents of the write address pointer 19 with the contents of the read address pointer 21 and generate an output signal to the status logic module 27 whenever the two comparator addresses are equal. This would indicate that for a particular memory location in the RAM 13 a read and a write operation are being requested simultaneously. It can also indicate that a full or empty memory condition has been detected.
  • the status logic module 27 performs two separate functions. First, it detects when either the address in the write address pointer register 19 or the read address pointer register 21 is at its maximum. This would signify either an addressing error or memory overflow for the RAM 13. Second, if the general purpose data buffer is in the RAM, FIFO, or shift-register modes, the status logic module 27 generates an output signal when the contents of the write address pointer register 19 and the read address pointer register 21 are equal. If the general purpose data buffer is in the stack accessing mode an output is generated when the contents of the read address pointer register 21 equals all high values.
  • the RAM address multiplexer 23 is coupled to the RAM 13 by RAM address bus 24.
  • the data input multiplexer 29 is coupled to both I/O port A 15 and I/O port B 17.
  • the data input multiplexer 29 selects the data input to the RAM 13 and to the length register 33 according to the direction input (DIR) to the control logic module 11.
  • DIR direction input
  • Data output register 31 is a nine-bit latch which enables the output from RAM 13 to propagate to its selected output ports 15,.17 when the clock signal PH2 is high.
  • the data output register 31 will not change its state when clock signal PH2 is low.
  • I/O port A 15 and I/O port B 17 are coupled to the data output register 31.
  • the I/O port A and B represent two of a plurality of tri-state output cells which are controlled by the direction signal (DIR) and output enable signal (OE) supplied to the control logic module 11.
  • DIR direction signal
  • OE output enable signal
  • the I/O ports are output-disabled by being held in a high impedance state.
  • data port B is held in its high impedance state and may be used as the data input port to the general purpose buffer.
  • data port A is enabled as the output port of the general purpose data buffer.
  • OE is high and DIR is also high
  • data port A is held in its high impedance state and may be used as the data input port for the RAM 13 while data port B will be enabled as the output port.
  • the masked length register 37 is a programmable register which will designate the length of the general purpose buffer when power-on occurs. This length is set a the manufacturing stage for the general purpose data buffer and can be changed from this value by reprogramming.
  • the length register 33 is loaded with data, from either port A or port B, which designates the load length when the general purpose data buffer is in either the FIFO or shift register mode.
  • the length register 33 can be set to any length from one to the maximum storage length of the RAM 13.
  • the length multiplexer 35 is coupled to both the length register 33 and the masked length register 37. This multiplexer is employed to select either the masked length or the programmed length as input to the write address pointer 19 or the read address pointer 21.
  • the masked length is selected.
  • the multiplexer switches to select the program length from register 33. The multiplexer will remain in this state until a further power-on signal reselects the masked length register 37.
  • PA ⁇ - PA8 PORT A CELLS PB ⁇ - PB8 PORT B CELLS
  • WAB ⁇ - WAB7 TOGGLE UP COUNT
  • the logical operation AND is signified by a ".” and the logical function OR is signified by a "+”.
  • the NOT logical operation is signified by the superscription of a mnemonic name.
  • the logic equations are grouped according to the module in which the equation is implemented. The logic equations and the mnemonic list should be consulted during the consideration of the logic diagrams which will be explained in later sections of the specification.
  • the general purpose data buffer receives external control inputs I ⁇ , I1 , and I2 and an external clock PH1.
  • the Control logic module I1 processes these inputs to produce internal control signals which determine the buffer mode of operations.
  • the following table sets forth the buffer operation selected for the various configurations of the instruction codes received on I ⁇ through I2.
  • the READ operation causes an instruction cycle which is dependent on which previous initialization instruction has been executed in the buffer. If the buffer has been initialized by a CLEAR or LOAD LENGTH instruction (STACK flip-flop reset), read address pointer register 21 will be incremented during the write phase and output register 31 will be loaded with the contents of the RAM location addressed by the read address register during the read phase. If the contents of write address pointer register
  • Operation during the WRITE cycle is also dependent on which previous initialization instruction has been executed. If the general purpose data buffer has been initialized by a CLEAR or a LOAD LENGTH instruction (the STACK flip-flop reset), the data from the input port, as defined by the state of DIR, will be loaded into the RAM location addressed by write address pointer register 19 during the write phase. The write address pointer register will be incremented during the read phase. If the contents of the write address pointer register 19 and the read address pointer register 21 are equal at the end of a WRITE cycle, the FULL flag in status logic module 27 will be set. If the buffer has been initialized by a STACK INITIALISE instruction, the buffer will operate exactly as for the SHIFT instruction which will be explained next.
  • the SHIFT instruction is a combination of the READ and WRITE instructions previously described.
  • the data from the input port (as defined by the state of DIR) will be loaded into the RAM location addressed by the write address pointer register 19, and the read address pointer register 21 will be incremented.
  • the contents of the location addressed by the read address pointer register 21 will be loaded into the output register 31, and the write address pointer register will be incremented.
  • the CLEAR instruction causes read address pointer register 21 and write address pointer register 19 to be set to the value of the data currently at the DIR-defined input port.
  • the EMPTY flag is set, and both the FULL flag and the STACK flip-flop are reset.
  • the resetting of the STACK flip-flop affects subsequent READ and WRITE instructions as previously explained.
  • the CLEAR instruction the contents of the location addressed by read address pointer register 21 will be loaded into the output register.
  • the write address pointer register will be set to "all zeros", and the read address pointer register will be set to "all ones”.
  • the STACK flip-flop will be set.
  • the LOAD LENGTH instruction causes read address pointer register 21, write address pointer register 19, and length register 33 to be loaded with the value of the data at the DIR-defined input port.
  • the EMPTY flag will be set, the FULL flag will be reset, and the STACK flip-flop will be reset.
  • a flip- flop within the general purpose data buffer will also be set to indicate that the buffer length has been set externally.
  • the RECIRCULATE instruction is analogous to the SHIFT instruction except that there is no loading of RAM 13.
  • the read address pointer register will be incremented during the write phase. During the read phase, the write address pointer register will be incremented while output register 31 will be loaded with the contents of the location addressed by the read address pointer register.
  • Figure 2 is a logic embodiment of control logic module 11 of Figure 1.
  • Load address pointers - signal L ⁇ is generated and supplied to the write address pointer register by combining I ⁇ and through inverter 103 and NOR gate 109. is generated by inverting LD with inverter 119.
  • the stack reset signal STKR is generated by NOR gate 111 from I ⁇ and .
  • the stack set signal STKS is the output of NOR gate 113 which combines I1, and 2
  • the write to RAM signal RWT is the output of AND gate 115.
  • An input to AND gate 115 is the external clock signal PH1 and the output of NOR gate 107 which combines 12 and .
  • a POP signal for reading from the RAM when it is in the stack mode is generated from NOR gate 117 combining I2, I1 and NSTCK.
  • the POP signal is provided as an output of the control circuit module I1 to the read address pointer register.
  • POP is inverted by inverter 127 to generate NPOP which is supplied to the read and write address-pointer registers.
  • the stack mode for the general purpose data buffer is selected by a flip-flop which is formed by NOR gates 131 and 133.
  • the output STCK supplies an input to NOR- gate 139 where it is combined with and
  • the STCK -signal is also provided to the status logic module and is ' an input to NOR gates 137 and 141.
  • NOR gate 137 combines STCK with and 12 to generate an output which is an input to NOR gate 145.
  • NOR gate 141 combines STCK, , and 12 to generate an input for NOR gate 147.
  • NOR gate 143 generates the PUSH signal which, when the general purpose data buffer is operating in the stack mode, designates that a new entry is to be placed into the stack.
  • the PUSH signal is combined in NOR gate 145 with the output of NOR gate 137 and NOR gate 139 to generate a signal which designates an increment in the read address pointer register.
  • the PUSH signal is combined by NOR gate 147 with the output of NOR gates 141 and 139 to generate a signal which increments the write address pointer.
  • NOR gate 129 receives I ⁇ , and and then generates the LPLR signal which initiates a load of the length register from one of the data ports.
  • the RAMWT signal is generated by inverter 135 and propagated to the data input multiplexer to signal a RAM write pulse.
  • Figure 3 presents logical embodiments for RAM address comparator 25 and RAM address multiplexer 23 as shown in Figure 1.
  • RAM address multiplexer 23 The components which make up the RAM address multiplexer are shown within the dashed portion of Figure 3 designated by the numeral 23, and the address comparator is shown within the box labelled 25.
  • RAM address multiplexer 23 a plurality of logic gates are provided in one-to-one correspondence with the addressing lines to the random access memory.
  • the logic gates receive as inputs RAi and from the read address pointe register and WAi and from the write address pointer register.
  • PH2 the inverse of external clock PH1
  • RA ⁇ the inverse of external clock PH1
  • RAMAD ⁇ The address in the former case is propagated out as RAMAD ⁇ and in the latter case as RAMAD ⁇ .
  • RAMAD ⁇ There are eight groups of these gates within random access multiplexer 23 for generating RAMAD ⁇ -RAMAD7 or These addresses are the result of outputs from the write address pointer register 19 and read address pointer register 21.
  • random address comparator 25 is employed for two purposes: first, to determine whether an attempt is being made to simultaneously access a particular memory location in random access memory 13 for both a read and a write operation, and second, to detect a full or empty memory condition.
  • Gates 211 and 213, together with inverter 215, are coupled to NOR gate 217.
  • the gates 211, 213, and 215 will propagate an EQUL ⁇ signal if both WA ⁇ and RA ⁇ are high or and R are high.
  • the EQUL signal is supplied to the status logic module 27 for generating appropriate output indication flags as previously explained.
  • the write address pointer register and the status logic module are shown in Figure 4.
  • the status logic module is enclosed within the dashed portion labeled 27 and generates the FLAG signal under certain conditions.
  • One of the conditions is when the buffer is in the STACK mode and all of the bits of the address of a read instruction are high.
  • the detection of this condition begins at NOR gate 273 where the bits RA7 of the read address for the random access memory are shown as inputs.
  • the output of NOR gate 273 is RAX which is supplied to the gate 283.
  • the STCK signal is routed to gate 283 from control logic module 11 and, if RAX and STCK are simultaneously high, a signal is generated which is inverted by inverter 287 to result in the FLAG signal.
  • the other condition in which the FLAG signal is generated is that in which the buffer is in any mode other than STACK and a read and write are simultaneously attempted on the same memory location.
  • gate 285 first combines NSTCK from control module 11 with EQUL (indicating that the read and write addresses are the same from address comparator 25. is then generated and supplied to inverter 287 for conversion into the desired signal.
  • the RAX signal from NOR gate 273 is also supplied to inverter 275 and then to NOR gate 279 where it is combined with INCR from control logic module 11.
  • the result of the combination by the NOR gate 279 is RRST or read address pointer reset. This is generated when an increment of the read address pointer is being requested simultaneously with the read address being at its maximum value.
  • the RAM address which is requested for a write operation is likewise examined to determine whether it is all ones. This is accomplished by
  • NOR gate 271 which combines to generate a WAX signal indicating that all of the address bits are high. WAX is supplied to write address pointer register 19 of
  • the write address pointer register is designated by block 19 in Figure 4.
  • the write address pointer register comprises eight individual circuit modules, each of which generate respective WA or outputs.
  • One such circuit module is illustrated by the logic device 301, AND gates 303 and 307, and NOR gates 305 and
  • circuit element 301 is schematically illustrated in Figure 5 which can be referred to for further details.
  • the "A" input of the module 301 indicates a toggle (down count) to the write address pointer cell. In the case of
  • this down count input is the POP signal from the control logic module.
  • the toggle signal is the result of the combination, via a NOR gate, of the NPOP signal from the control logic module together with the signal WAj (0 ⁇ j ⁇ i). [grate: no "-" before "i” .
  • the "B" input to logic element 301 is the output of a combination in NOR gate 309 of the signal from the control logic module and WAX from the status logic module. For the seven remaining modules WAi (1 ⁇ j ⁇ 7), the signals (0 ⁇ j ⁇ i) are also included in the NOR gate combination.
  • the "C” input to each of the logic modules is used to reset the given write address pointer cell.
  • the “C” input is generated from an AND gate (303 in the case of. WA ⁇ ) which receives a WRST signal from the status module and an LENi signal from the data input multiplexer and length register.
  • the "D” input to all of the modules is STKS from the control logic module. By simultaneously resetting each of the write address pointer cells to zero, STKS thus resets the entire write address to zero.
  • the "E” input to the logic cell 301 is the output of NOR gate 305 and sets the data input to the write address pointer cell. This is generated by NOR gate 305 combining the and signals.
  • the signal is generated by DI/LR ⁇ in the data input multiplexer.
  • the "F” input to WAO 301 is generated by AND gate 307 which combines and LD.
  • the LD signal causes a load of the address pointer register and the "F” input to cell 301 corresponds to the "C” input of RA0 in the read address pointer register.
  • the "G" input to the address cell 301 is the clock signal PH2.
  • the output of register cell 301 is either WA1 or which reflect the address within the RAM which is being accessed for a memory write.
  • Figure 5 is a logical implementation of the cells in the write address pointer register labeled 301 in Figure 4.
  • One skilled in the art would be able to follow the input signals "A” through “G” previously explained in the module 301 to see how the outputs WA. and WAi are generated. It is felt that a more further explanation of the cell as shown in Figure 5 is not required.
  • Figure 6 shows a logical embodiment of the mask length selector 37 the length register 33, the length multiplexer 35 and the data input multiplexer 29.
  • the masked length comprises the switches 600-607 depicted in the portion of Figure 6 labeled 37.
  • the switches enable the masked length to be selected from one to eight bits long by placing the programmable switch such that Vcc is connected to the switch terminal rather than ground.
  • the length multiplexer comprises eight sets of gates such as 611 and 613 which form length code cells LENO- -LEN7 . These length cells are suitably connected to the write address pointer register as previously explained. The cells are set to a high condition when the switches in the mask length register 37 are appropriately thrown or there is an output from the program length register 33. These outputs are labeled PLi (0 ⁇ i ⁇ 7) and are coupled by switches to the output from the flip-flop formed from NOR gates 615 and 617 to generate LENi.
  • the NOR gate 615 has as one input the power ON signal and the other input is the output of NOR gate 617.
  • NOR gate 617 has as one input the output of NOR gate 615 and the LLP signal (pulsed low length register). LLP is generated by AND gate 619 which combines the PHI clock signal with LPLR from the control module 11.
  • the logical elements embodied within the hatched portion labeled 33 comprise both the data input multiplexer and the masked length register.
  • the DIR is an external signal which designates which data port is supplying the data and which is to receive the data. DIR is supplied as an input to each of the register modules 621 shown in Figure 6. Another input to the modules is the complement which is supplied by inverter 631.
  • the DIR and signals respectively comprise the C and D inputs to the register cells 621.
  • the B input is RAMWT which is a RAM write pulse from the control logic module 11.
  • the F input to the register cells 621 comprises the LLP signal previous defined as the pulse to low length register and the G input to the memory cells comprises the LLP signal from inverter 608.
  • the B input to the register cell 621 is coupled to port A such that the B input to DI/LRi (0 ⁇ i ⁇ 7) comprises the PAi signal from port A.
  • the E input to DI/LR (0 ⁇ i ⁇ 7 ) is coupled to port B and is the PBi signal.
  • Figure 7 shows the logical circuit elements which are employed to fabricate each of the register cells 621
  • the DTi (0 ⁇ i ⁇ 7) designates a data input to cell I within the address pointer registers
  • RAMOi (0 ⁇ i ⁇ 7) is the data path to random access memory 13.
  • the (0 ⁇ i ⁇ 7) is also supplied as a data input to the RAM 13
  • the PLi signal (0 ⁇ i ⁇ 7) is, as previously mentioned an input to the length register 35.
  • the NRAMI08 and the RAMI08 signals are generated by logic gates 641 and 643 and inverters 645-651.
  • Figure 8 is a logical embodiment of the read address pointer register designated 21 in Figure 1.
  • the read address pointer register is an 8-bit binary up/down counter with parallel load facilities.
  • the read address pointer register addresses the RAM when data is being read inputs are generated by a series of AND gates 807 which generate the RAE i signals (0 ⁇ i ⁇ 7) by combining the read address pointer reset signal RRST from the status logic module with the length signal LEN i from the length multiplexer of Figure 6.
  • the F input to the circuit modules RA i is the RAF i signal defined as LD.DI i (0 ⁇ i ⁇ 7). This signal is also supplied to the E inputs of the circuit modules WA i in the previously explained write address pointer register.
  • the G input to the circuit modules RA i is the signal RAG i and is equal to the PH1 clock signal.
  • Figure 9 is an implementation of each of the read address register cells RA i (0 ⁇ i ⁇ 7) which combines the read address pointer register.
  • the inputs A though G to each of the register cells have been previously explained in conjunction with Figure A and it is felt that one skilled
  • Figures 10A and 10B show the logical embodiment of the data output register 31, the port A logic 15 and port B logic 17 as shown in block diagram form in Figure 1.
  • the port A logic comprises a plurality of port A cells 1001 which are designated PTA i (0 ⁇ i ⁇ 7) .
  • the port B 10 logic 17 comprises a plurality of port B cells 1005 designated PTB i (0 ⁇ i ⁇ 7).
  • the output register comprises a plurality of output register cells 1003 designated OR i (0 ⁇ i ⁇ 7).
  • the read address pointer register can be loaded with external data from either port A or port B or with contents of the program length register or the mask length. The data from either port A or port B would normally comprise an address within the RAM.
  • the read address pointer register comprises a plurality of circuit modules RA0-RA7.
  • the output of the read address pointer registers are an address within the RAM designated RA0-RA7 or
  • the read address pointer register receives the NPOP and POP signals from the control logic module 11.
  • the POP signal is supplied to the A input of circuit module RA0 whose Q output is connected to the signal line RA0.
  • the remaining A inputs of the circuit modules RA i (1 ⁇ i ⁇ 7) receive the logical NOR of RA i (0 ⁇ j ⁇ i) and NPOP.
  • the Q outputs for the circuit modules RA0-RA7 are all connected to an associated signal line RA0-RA7, respectively.
  • RAAi POP ⁇ RAO ⁇ RA1 ⁇ ⁇ ⁇ RA (I-1) (0 ⁇ i ⁇ 7).
  • the B input to the circuit modules RA. is the RAB. signal whose logic equation is INCR ⁇ RAX ⁇ RAO ⁇ RA1 ⁇ ⁇ ⁇ RA(i-1) for 0 ⁇ i ⁇ 7.
  • the RAB i signals are generated by the NOR gates 805 associated with the circuit modules.
  • the C input to the circuit modules RA. is defined by the signal RAC i which equals LD;DI i (0 ⁇ i ⁇ 7).
  • the DI i signal is provided from the data input multiplexer previously described in Figure 6.
  • the D input to the circuit modules RA i comprises the stack set signal STKS from the control logic module 11.
  • the E cells 1003 are respectively shown in Figures 11A, 11B and
  • the port A cell PTA i each receive inputs A through F and generate an output PA. (0 ⁇ i ⁇ 8).
  • the A input is connected to the voltage source V and the B input is the BTA signal signifying the data flow direction as being from port B to port A.
  • BTA is generated by NOR gate 1001 which combines the direction signal DIR and the complement of the output enable signal OE as provided from inverter 1009.
  • the C inputs to the port A cells PTA i correspond to the OR i outputs of the output registers OR i .
  • the D input is the BTA signal inverted by inverter 1001 and the E input is the OR i signal which is the Q output of the output register cell OR i (0 ⁇ i ⁇ 7).
  • the F inputs of all the port A cells are tied to ground.
  • the port B logic is designated as 17 in Figures 10A and 10B.
  • the operation of the individual circuit modules 1005 corresponding to PTB0-PTB8 is very similar to the operation of the previously described circuit modules PTA0-PTA8.
  • the circuit modules generate an output PBI (0 ⁇ i ⁇ 8) which as previously explained are inputs to the circuit modules DI/LRi in the data input multiplexer.
  • the A inputs of all the circuit modules are tied to the voltage source V cc and the B inputs are the directional inputs ATB translated as A to B . This means that the A port is on input and the B port is on output when the ATB is high.
  • the ATB signal is generated by NOR gate 1021 which combines the OE signal from inverter 1009 and the
  • the C inputs to the circuit modules PTBi are identical to the C inputs to the circuit modules PTA i .
  • This signal is the signal from the output register circuit modules ORi.
  • the D input correspond to the inverse of the ATB signal generated by inverter 1023.
  • the E inputs to the circuit modules are identical to the E inputs to the port A circuit modules OR i generated by the Q output of the output register modules OR i .
  • the F inputs are tied to ground.
  • the output register is identified as 31 in Figures 10A and 10B.
  • the logical implementation of the output register circuit modules OR i is given in Figure 11C and is easily understood by one skilled in the art.
  • the output circuit modules OR i generate signals OR i and O (0 ⁇ i ⁇ 8) which as previously explained are inputs to the port A and port B circuit modules.
  • the A input to the output register circuit modules is the signal RAMIOi from the dat input multiplexer.
  • the B inputs all equal the PH2 clock signal and the C inputs are the inverse of the PH2 clock signal generated by inverter gate 1025.
  • Figure 12 schematically shows a suitable random access memory for use with the disclosed general purpose data buffer. While the RAM memory shown in Figure 12 is 256 9-bit words, one skilled in the art would understand that larger and smaller memories could be employed.
  • the inputs and output data from the random access memory comprise the signals NRAMIOO-NRAMI08 and RAMIO0-RAMIO8.
  • the address lines to the RAM comprise RAMAD0-RAMAD7 and R from the RAM address multiplexer shown in Figure 3.
  • the instruction inputs 10-12 are initially set to CLEAR.
  • the address to be written into within the RAM is provided to the write address pointer register and the clock cycle is generated to load the address into the write address pointer register.
  • the instruction input to the control logic module is set to WRITE and the data input flag is set.
  • a clock cycle is generated to load the data bite into the RAM from whichever of the data ports has been selected by DIR to be an input port.
  • the data input is continuously set in the clock cycles for loading the data are generated for many bites of data as are desired to be loaded into the random access memory.
  • the instruction inputs to the control logic module are set to CLEAR and the address is provided by the data port which DIR indicates is to receive the data from the RAM.
  • a clock cycle is generated to load the address into the read address pointer register and the instruction input to the control logic module is set to READ.
  • Another clock cycle is generated to read the data from the RAM and transfer to the output register and to the output data port.
  • Successive clock cycles are generated for each bite of data which is to be read from the RAM.
  • the instruction inputs I0-I2 to the control logic module are set to CLEAR.
  • a clock cycle is generated to clear the FIFO buffer and the instruction input 10-12 is set to WRITE.
  • the data input is set and a clock cycle is generated to load the data bite into the buffer which is being operated in the FIFO_ module.
  • the data bite is supplied by the data port which DIR has selected as the input port.
  • the instruction inputs to the control logic module are set to READ and clock cycles are generated to transfer data characters from the RAM to the output register and the output data port.
  • the instruction inputs 10, 12 are set to LOAD LENGTH.
  • the data input from the port. selected by DIR is set to equal the 2's complement of the required length and a clock cycle is generated to set tha length into the length register 33.
  • the data inputs I0-I2 are set to SHIFT and a data input is set from the port supplying the data as indicated by DIR.
  • a clock cycle is generated to shift the information in the RAM (which is being operated in the shift register mode) one position and successive clock cycles may be generated to further shift the information.
  • To recirculate the information in the shift register the inputs I0-I2 are set to recirculate and clock cycles are successively generated to recirculate the information.
  • the instruction inputs I0-I2 to the control logic module are set to INITIALISE and a clock cycle is generated.
  • the instruction inputs are then set to WRITE and the data inputs are supplied by the input ports selected by DIR. End clock cycles equal in number to the number of stages in the stack, are generated to push or load data from the input data port.
  • the instruction inputs are set to READ and clock pulses are generated for each position within the stack that the information is to be popped.
  • a push or write instruction is executed the data from the input port will be loaded into the top location in the stack and the data characters already in the stack will be pushed down one location in the RAM. If 256 pushes have been executed FLAG will be set.
  • the forgoing describes the acritecture and operation of a general purpose data buffer for the temporary storage of data transferred between two or more bidirectional data ports sharing the general purpose data buffer.
  • the general purpose data buffer is selectably operable in a random access mode, by a first-in-first-out upper mode, shift register mode and a stack accessing mode.
  • a practical application of such a general purpose data buffer is within peripheral controllers to replace conventional data storage devices with this multi-mode flexible buffer.
  • the general purpose data buffer incorporates a control logic module for selecting the mode of buffer operation as well as enabling the output and selecting a data port for input and a data port for output.
  • a random access memory is employed for temporarily storing the data to be transferred to and from the selective ports.
  • the read address pointer register and a right address pointer register are coupled with a random access comparator and a random access multiplexer for accessing selected locations in the random access memory. Certain accessing and storing conditions are detected by a status logic module and flags are according set.
  • the random access memory receives data from a selected data port through data input multiplexer and transfers data to a selected port through a data output register. Each data port has its appropriate data module for controlling the transfer of data between the port and random access memory.
  • the general purpose data buffer further includes a length register, a max-length selector and a length multiplexer for establishing the length of the data information to be transferred to or from the random access memory.

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  • Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Mathematical Physics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Static Random-Access Memory (AREA)

Abstract

Un tampon de donnees a usages multiples sert au stockage et au transfert de donnees entre une paire selectionnee parmi une pluralite de point d'acces de donnees suivant un mode selectionne parmi une pluralite de modes y compris un mode premier entre-premier sorti, un mode dernier entre premier sorti et un mode a acces selectif.
EP19800900984 1979-06-05 1980-12-15 Tampon de donnees a usages multiples Withdrawn EP0029834A1 (fr)

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GB7919511 1979-06-05
GB7919511 1979-06-05

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EP0029834A1 true EP0029834A1 (fr) 1981-06-10

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WO (1) WO1980002755A1 (fr)

Families Citing this family (8)

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Publication number Priority date Publication date Assignee Title
FR2496314A1 (fr) * 1980-12-12 1982-06-18 Texas Instruments France Procede et dispositif pour permettre l'echange d'information entre des systemes de traitement d'information a vitesses de traitement differentes
JPS588348A (ja) * 1981-07-07 1983-01-18 Sony Corp 出力表示用メモリの制御回路
JPS58154054A (ja) * 1982-03-10 1983-09-13 Hitachi Ltd 外部記憶装置制御用回路
US4949301A (en) * 1986-03-06 1990-08-14 Advanced Micro Devices, Inc. Improved pointer FIFO controller for converting a standard RAM into a simulated dual FIFO by controlling the RAM's address inputs
US5133062A (en) * 1986-03-06 1992-07-21 Advanced Micro Devices, Inc. RAM buffer controller for providing simulated first-in-first-out (FIFO) buffers in a random access memory
US5255359A (en) * 1989-10-23 1993-10-19 International Business Machines Corporation Picking function for a pipeline graphics system using hierarchical graphics structures
FR2717922B1 (fr) * 1994-03-24 1996-06-07 Master K Procédé et dispositif de transfert de données entre un indicateur de pesage et une unité centrale de traitement de données.
EP0945786B1 (fr) * 1998-03-27 2004-02-18 Motorola, Inc. Dispositif et procédé d'exécution d'instructions chiffrées

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DE2517565C3 (de) * 1975-04-21 1978-10-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Schaltungsanordnung für ein Datenverarbeitungssystem
JPS5247636A (en) * 1975-10-15 1977-04-15 Toshiba Corp Control method for transmitting information
JPS5255446A (en) * 1975-10-31 1977-05-06 Toshiba Corp Information transfer control system

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See references of WO8002755A1 *

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