Classifications

• • H—ELECTRICITY
  • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
  • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
  • H05K7/00—Constructional details common to different types of electric apparatus
  • H05K7/02—Arrangements of circuit components or wiring on supporting structure
  • H05K7/10—Plug-in assemblages of components, e.g. IC sockets
  • H05K7/1015—Plug-in assemblages of components, e.g. IC sockets having exterior leads
  • H05K7/103—Plug-in assemblages of components, e.g. IC sockets having exterior leads co-operating by sliding, e.g. DIP carriers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/40—Leadframes
  • H10W70/451—Multilayered leadframes
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
  • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W76/00—Containers; Fillings or auxiliary members therefor; Seals
  • H10W76/10—Containers or parts thereof
  • H10W76/12—Containers or parts thereof characterised by their shape
  • H10W76/15—Containers comprising an insulating or insulated base
  • H10W76/157—Containers comprising an insulating or insulated base having interconnections parallel to the insulating or insulated base
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/075—Connecting or disconnecting of bond wires
  • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
  • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/50—Bond wires
  • H10W72/541—Dispositions of bond wires
  • H10W72/547—Dispositions of multiple bond wires
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
  • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
  • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
  • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Definitions

• This invention relates to integrated circuit packages of the kind having a plurality of pins for providing external electrical connections.
• an integrated circuit package of the kind specified characterized in that at least one of said pins includes a plurality of conductors so that a plurality of external electrical connections are made at said one of said pins.
• Fig. 1 is a perspective view of one embodiment of the present invention, including an integrated circuit package and external connectors for engaging each pin on the integrated circuit package.
• Fig. 2 is the same view as Fig. 1, with the external connectors removed and with portions of the integrated circuit package broken away to expose details thereof.
• Fig. 3 is a sectional view taken along the line III-III of Fig. 2.
• Fig. 4 is a perspective view illustrating a • second embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package.
• Fig. 5 is a perspective view illustrating a third embodiment of the present invention, including a portion of an integrated circuit package and a connector for engaging a pin on the integrated circuit package.
• Fig. 6 is a sectional view taken along the line VI-VI of Fig. 5.
• the integrated circuit package 10 includes a body or housing 12 and a plurality of pins 14 depending from the sides of the housing.
• the housing 12 supports and encloses a semi ⁇ conductor or integrated circuit chip (not shown in Fig. 1) that can have a large number of circuit components fabricated thereon for performing logic, processing, memory or other functions.
• a semi ⁇ conductor or integrated circuit chip (not shown in Fig. 1) that can have a large number of circuit components fabricated thereon for performing logic, processing, memory or other functions.
• the present invention is not concerned with the nature of the integrated circuit chip itself, it being understood that such a chip could be ma"de in any one of many con ⁇ ventional techniques for performing any one of many conventional functions.
• the integrated circuit package could be used in a computer or any other type of electronic or electrical system.
• the housing 12 in Fig. 1 has three package layers, including a cap or top layer 20, a thin middle - layer 22, and a bottom or support layer 24. As can be seen, the middle layer 22 overlies the bottom layer 24, and the top layer 20, in turn, overlies the middle layer 22.
• the pins 14 generally depend from the housing 12 at the middle layer 22, and are each constructed so as to have an elongate insulating member or substrate 30 with conductive material located to form two conductors' 32 and 34, the conductors spaced apart with one on each of two opposing sides of the insulating member 30. As will be described in greater detail later with reference to Fig. 2, the insulating member 30 of each pin 14 may be integral with the layer 22 of the housing 12.
• pin conductors 32 and 34 may be integral with conductive patterns or leads 40 (shown only in Fig. 2) that are located on each side of * the package layer 22 and that permit access to the in ⁇ tegrated circuit chip- within the housing 12 for purposes of transferring or carrying signals to and from the in ⁇ tegrated circuit chip.
• a connector assembly 0 for use with the integrated circuit package 10 includes a plurality of connectors 42 that are positioned or aligned so as to each receive one of the pins 14.
• Each connector 42 includes two opposing contacts 46 and 48, with each of the contacts 46 and 48 having an arcuate pin-engaging end 50 for making electrical contact with one of the conductors 32 and 34 on each pin 14.
• Each of the contacts 46 and 48 may be connected to external power, data, address or other signal lines (not shown) .
• Figs. 2 and 3 there is shown in greater detail the construction of the integrated circuit package 10.
• each of the pin conductors 32 and 34 is formed integrally with and, hence, electrically connected to one of the previously- mentioned conductive leads 40 that are positioned on each side of the package layer 22.
• the conductive leads 40 all converge to an opened center portion 56 (Fig. 3) . of the housing 12 formed by the middle package layer 22 and enclosed by the top and bottom package layers 20 and 24.
• An integrated circuit chip 60 is mounted on layer 24 at the opened portion 56 so that, as conven ⁇ tional, connecting wires 62 may electrically connect each conductive lead 40 to an electrode or pad on the chip 60.
• the package layers 20, 22 and 24 may be formed in a conventional fashion from ceramic, plastic or other insulating or dielectric material.
• the conductive leads 40 may likewise be formed in a conventional fashion, for example, by being stamped from a conductive sheet as a lead frame and then suitably bent and milled to form each one of the leads 40 and conductors 32 and 34.
• other suitable forms of constructing the inte- grated circuit package 10 could be employed, such as molding the entire housing 12 about the chip 60 as a single piece.
• the leads 40 in the conductive layers 32 and 34 could be formed using a printed circuit board process, by starting with a relatively thin (.1 mm) dielectric base, as the layer 22, and then depositing* conductive material on both sides of the base to form the leads 40 and conductors 32 and 34.
• the base could be then milled to form projections having the conductors 32 and 34 thereon, and the projections could be heated and bent to form the pins 14.
• the chip could then be mounted and electrically connected, and then the package capped or encapsulated in plastic to form the finished integrated circuit package 10.
• Figs. 1, 2 and 3 is able to provide twice as many exter ⁇ nal electrical connections as there are pins 14. More particularly, as seen best in Figs. 1 and 2, by spacing the conductors 32 and 34 at each pin 14 in a direction that is generally perpendicular to the direction in which the pins are spaced along each side of the housing 12, the integrated circuit package 10 is made to occupy no more area than a conventional integrated circuit package having the same number of pins but only half as many external connections.
• the number of electrical connections could be an even higher multiple of the number of pins than that illustrated in Figs. 1, 2 and 3, by increasing the number of conductors at each pin by, for example, employing the structure to be described in greater detail below with reference to the embodiments illustrated in Figs. 4 and 5.
• the integrated circuit package 10 is shown as being in the form of a dual-in-line package (DIP), the present invention is, of course, not so limited.
• the pins 14 could be constructed as shown in Figs. 1, 2 and 3, but depend from a single- in-line package (SIP), or depend on all four sides of an integrated circuit housing.
• the integrated circuit 110 includes a housing 112 having depending pins, with only one pin 114 shown in Fig. 4.
• the pin 114 includes three overlying, elongate insulating members or substrates, comprised of an inner insulating member 130B and two outer insulating members 130A and 130C.
• The- pin 114 further includes four con- ductors 131, 132, 133, and 134, that are separated by the insulating members.
• Conductor 131 is located on the outside surface of member 130A
• conductor 132 is located between the inside surface of member 130A and the con ⁇ fronting surface of member 13OB
• conductor 133 is located between the inside surface of member 130C and the con ⁇ fronting surface of member 130B
• conductor 134 is located on the outside surface of member 130C.
• Insula ⁇ ting member 130B has a portion extending beyond the in ⁇ sulating members 130A and 130B, so that conductors 132 and 133 are exposed at the end of the pin.
• the pin 114 on the integrated circuit package 110 provides four external electrical connections to the integrated circuit chip (not shown in Fig. 4) within the housing 112.
• a connector 142 for engaging the pin 114 is shown, in Fig. 4 as having four contacts, including two inner contacts 145 and 146, and two outer contacts 147 and 148.
• Each of the contacts 145, 146, 147 and 148 has an arcuate pin engaging end 150, with the ends 150 of contacts 145 and 146 recessed so that they engage the exposed portions of conductors 132 and 133, and so that the ends 150 of contacts 147 and 148 will engage the conductors 131 and 134.
• Figs. 5 and 6 there is shown a portion of an integrated circuit package 210, illustrating yet a further embodiment of the present invention.
• the inte ⁇ grated circuit package 210 includes a housing 212 having depending pins, with only one pin 214 shown in Fig. 5.
• the pin 214 includes an insulating member or substrate 230 having a substantially square cross-sectional shape, as seen best in Fig. 6.
• Four conductors 231, 232, 233 and 234 are formed respectively on the four sides of the insulating member 230, so that the pin 214 can provide four external electrical connections.
• a connector 242 for engaging the pin 214 is also shown in Fig. 5, and includes four contacts 245, 246, 247 and 248. Each of the contacts 245, 246, 247 and 248 has an arcuate pin engaging end 250 for engaging one of the conductors 231, 232, 233 and 234.

Landscapes

• Engineering & Computer Science (AREA)
• Microelectronics & Electronic Packaging (AREA)
• Connecting Device With Holders (AREA)

Applications Claiming Priority (2)

Publications (1)

Family

ID=22526542

Family Applications (1)

Country Status (4)

Families Citing this family (7)

Family Cites Families (3)

• 1981
  • 1981-04-30 ZA ZA00812893A patent/ZA812893B/xx unknown
  • 1981-05-04 EP EP81901454A patent/EP0051666A1/de not_active Withdrawn
  • 1981-05-04 WO PCT/US1981/000610 patent/WO1981003396A1/en not_active Ceased
  • 1981-05-11 BE BE0/204752A patent/BE888756A/fr unknown

Non-Patent Citations (1)

Also Published As

Similar Documents

Legal Events