EP0192578A3 - Système à bus multiple comprenant un microprocesseur ayant des interfaces et des antémémoires séparées d'instructions et de données - Google Patents

Système à bus multiple comprenant un microprocesseur ayant des interfaces et des antémémoires séparées d'instructions et de données Download PDF

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Publication number
EP0192578A3
EP0192578A3 EP86400365A EP86400365A EP0192578A3 EP 0192578 A3 EP0192578 A3 EP 0192578A3 EP 86400365 A EP86400365 A EP 86400365A EP 86400365 A EP86400365 A EP 86400365A EP 0192578 A3 EP0192578 A3 EP 0192578A3
Authority
EP
European Patent Office
Prior art keywords
data
bus
instruction
coupled
cache
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP86400365A
Other languages
German (de)
English (en)
Other versions
EP0192578A2 (fr
Inventor
Howard Gene Sachs
Walter H. Hollingsworth
James Youngsae Cho
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intergraph Corp
Original Assignee
Intergraph Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intergraph Corp filed Critical Intergraph Corp
Publication of EP0192578A2 publication Critical patent/EP0192578A2/fr
Publication of EP0192578A3 publication Critical patent/EP0192578A3/fr
Withdrawn legal-status Critical Current

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Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/08—Addressing or allocation; Relocation in hierarchically structured memory systems, e.g. virtual memory systems
    • G06F12/0802—Addressing of a memory level in which the access to the desired data or data block requires associative addressing means, e.g. caches
    • G06F12/0844—Multiple simultaneous or quasi-simultaneous cache accessing
    • G06F12/0846—Cache with multiple tag or data arrays being simultaneously accessible
    • G06F12/0848—Partitioned cache, e.g. separate instruction and operand caches

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
  • Multi Processors (AREA)
EP86400365A 1985-02-22 1986-02-21 Système à bus multiple comprenant un microprocesseur ayant des interfaces et des antémémoires séparées d'instructions et de données Withdrawn EP0192578A3 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US70456885A 1985-02-22 1985-02-22
US704568 1985-02-22

Publications (2)

Publication Number Publication Date
EP0192578A2 EP0192578A2 (fr) 1986-08-27
EP0192578A3 true EP0192578A3 (fr) 1990-04-25

Family

ID=24830042

Family Applications (1)

Application Number Title Priority Date Filing Date
EP86400365A Withdrawn EP0192578A3 (fr) 1985-02-22 1986-02-21 Système à bus multiple comprenant un microprocesseur ayant des interfaces et des antémémoires séparées d'instructions et de données

Country Status (3)

Country Link
EP (1) EP0192578A3 (fr)
JP (1) JPS6237752A (fr)
CA (1) CA1269176A (fr)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2200483B (en) * 1987-01-22 1991-10-16 Nat Semiconductor Corp Memory referencing in a high performance microprocessor
JPS63220342A (ja) * 1987-03-10 1988-09-13 Fujitsu Ltd ブロツクアクセス方式
US4876651A (en) * 1988-05-11 1989-10-24 Honeywell Inc. Digital map system
US5148536A (en) * 1988-07-25 1992-09-15 Digital Equipment Corporation Pipeline having an integral cache which processes cache misses and loads data in parallel
JPH0711793B2 (ja) * 1989-07-13 1995-02-08 株式会社東芝 マイクロプロセッサ
JP3623379B2 (ja) * 1998-12-01 2005-02-23 富士通株式会社 マイクロプロセッサ
US6584546B2 (en) 2001-01-16 2003-06-24 Gautam Nag Kavipurapu Highly efficient design of storage array for use in first and second cache spaces and memory subsystems
US10649775B2 (en) * 2013-07-15 2020-05-12 Texas Instrum Ents Incorporated Converting a stream of data using a lookaside buffer

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075714A2 (fr) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Système d'antémémoire de microprocesseur sur microplaquette et procédé de fonctionnement

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0075714A2 (fr) * 1981-09-30 1983-04-06 Siemens Aktiengesellschaft Système d'antémémoire de microprocesseur sur microplaquette et procédé de fonctionnement

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
ELECTRONICS INTERNATIONAL, vol. 55, no. 16, August 1982, pages 112-117, New York, US; P. KNUSDEN: "Sumpermini goes multiprocessor route to put it up front in performance" *
THE 10TH ANNUAL INTERNATIONAL SYMPOSIUM ON COMPUTER ARCHITECTURE, ACM 1983, pages 108-116, New York, US; PATTERSON et al.: "Architecture of a VLSI instruction cache for a RISC" *

Also Published As

Publication number Publication date
EP0192578A2 (fr) 1986-08-27
CA1269176A (fr) 1990-05-15
JPS6237752A (ja) 1987-02-18

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Inventor name: SACHS, HOWARD GENE

Inventor name: CHO, JAMES YOUNGSAE

Inventor name: HOLLINGSWORTH, WALTER H.