EP0244367A3 - Integriertes Halbleiterbauelement des MOS-Typs mit einer nicht gleichförmigen Oxidsteuerelektrode und Verfahren zu seiner Herstellung - Google Patents

Integriertes Halbleiterbauelement des MOS-Typs mit einer nicht gleichförmigen Oxidsteuerelektrode und Verfahren zu seiner Herstellung Download PDF

Info

Publication number
EP0244367A3
EP0244367A3 EP87830113A EP87830113A EP0244367A3 EP 0244367 A3 EP0244367 A3 EP 0244367A3 EP 87830113 A EP87830113 A EP 87830113A EP 87830113 A EP87830113 A EP 87830113A EP 0244367 A3 EP0244367 A3 EP 0244367A3
Authority
EP
European Patent Office
Prior art keywords
gate oxide
fabricating
semiconductor device
integrated semiconductor
mos type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP87830113A
Other languages
English (en)
French (fr)
Other versions
EP0244367A2 (de
Inventor
Paolo Picco
Tiziana Cavioni
Alfonso Maurelli
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics SRL
Original Assignee
SGS Microelettronica SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SGS Microelettronica SpA filed Critical SGS Microelettronica SpA
Publication of EP0244367A2 publication Critical patent/EP0244367A2/de
Publication of EP0244367A3 publication Critical patent/EP0244367A3/de
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0144—Manufacturing their gate insulating layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/8314—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET] the IGFETs characterised by having gate insulating layers with different properties

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Non-Volatile Memory (AREA)
EP87830113A 1986-04-21 1987-03-25 Integriertes Halbleiterbauelement des MOS-Typs mit einer nicht gleichförmigen Oxidsteuerelektrode und Verfahren zu seiner Herstellung Withdrawn EP0244367A3 (de)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
IT83616/86A IT1191558B (it) 1986-04-21 1986-04-21 Dispositivo a semiconduttore integrato di tipo mos con spessore dell'ossido di porta non uniforme e procedimento di fabbricazione dello stesso
IT8361686 1986-04-21

Publications (2)

Publication Number Publication Date
EP0244367A2 EP0244367A2 (de) 1987-11-04
EP0244367A3 true EP0244367A3 (de) 1989-06-14

Family

ID=11323184

Family Applications (1)

Application Number Title Priority Date Filing Date
EP87830113A Withdrawn EP0244367A3 (de) 1986-04-21 1987-03-25 Integriertes Halbleiterbauelement des MOS-Typs mit einer nicht gleichförmigen Oxidsteuerelektrode und Verfahren zu seiner Herstellung

Country Status (3)

Country Link
EP (1) EP0244367A3 (de)
JP (1) JPS62252164A (de)
IT (1) IT1191558B (de)

Families Citing this family (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR910005395B1 (ko) * 1988-08-17 1991-07-29 삼성전관 주식회사 Ccd형 고체촬영소자의 스미어 특성 측정장치
JP2596117B2 (ja) * 1989-03-09 1997-04-02 富士電機株式会社 半導体集積回路の製造方法
IT1252025B (it) * 1991-11-29 1995-05-27 Sgs Thomson Microelectronics Procedimento per la realizzazione di celle di memoria a sola lettura programmabili e cancellabili elettricamente a singolo livello di polisilicio
EP0610643B1 (de) * 1993-02-11 1997-09-10 STMicroelectronics S.r.l. EEPROM-Zelle und peripherer MOS-Transistor
JP3163839B2 (ja) * 1993-05-20 2001-05-08 富士電機株式会社 半導体集積回路
US5595922A (en) * 1994-10-28 1997-01-21 Texas Instruments Process for thickening selective gate oxide regions
JPH10308497A (ja) * 1997-05-08 1998-11-17 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2000003965A (ja) 1998-06-15 2000-01-07 Mitsubishi Electric Corp 半導体装置およびその製造方法
JP2000315733A (ja) * 1999-04-28 2000-11-14 Fujitsu Ltd 多電源半導体装置の製造方法
US7184315B2 (en) * 2003-11-04 2007-02-27 Micron Technology, Inc. NROM flash memory with self-aligned structural charge separation

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2080024A (en) * 1980-06-30 1982-01-27 Hitachi Ltd Semiconductor Device and Method for Fabricating the Same

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2080024A (en) * 1980-06-30 1982-01-27 Hitachi Ltd Semiconductor Device and Method for Fabricating the Same

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
IEEE JOURNAL OF SOLID-STATE CIRCUITS *
PATENT ABSTRACTS OF JAPAN *

Also Published As

Publication number Publication date
IT1191558B (it) 1988-03-23
IT8683616A0 (it) 1986-04-21
EP0244367A2 (de) 1987-11-04
JPS62252164A (ja) 1987-11-02

Similar Documents

Publication Publication Date Title
GB1430301A (en) Method of manufacturing mos matrix circuits
EP0952611A3 (de) Halbleiteranordnung
GB2174244B (en) A method of manufacturing a bipolar transistor
EP0244367A3 (de) Integriertes Halbleiterbauelement des MOS-Typs mit einer nicht gleichförmigen Oxidsteuerelektrode und Verfahren zu seiner Herstellung
HK69587A (en) Semiconductor integrated circuit devices and method of manufacturing the same
EP0231811A3 (en) Method for manufacturing integrated electronic devices, in particular high voltage p-channel mos transistors
JPS56165359A (en) Semiconductor device
JPS56165358A (en) Semiconductor device
JPS57166071A (en) Semiconductor device
JPS56150864A (en) Semiconductor device
JPS6441258A (en) Semiconductor integrated circuit
JPS5522878A (en) Insulation gate type field effect semiconductor device
JPS6465875A (en) Thin film transistor and manufacture thereof
JPS6464364A (en) Semiconductor device and its manufacture
JPS6481359A (en) Mos type semiconductor integrated circuit device
JPS5339087A (en) Integrated circuit
JPS52146568A (en) Production of silicon gate mos type semiconductor integrated circuit device
JPS6425574A (en) Manufacture of semiconductor device
JPS5740973A (en) Inverter circuit and manufacture therefor
JPS5346287A (en) Production of semiconductor integrated circuit
JPS57211767A (en) Mos integrated circuit
JPS56133869A (en) Mos type semiconductor device and manufacture thereof
JPS57132368A (en) Semiconductor device
JPS57115858A (en) Semiconductor device
EP0414013A3 (en) Method for forming bipolar transistor in conjunction with complementary metal oxide semiconductor transistors

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB NL

PUAL Search report despatched

Free format text: ORIGINAL CODE: 0009013

AK Designated contracting states

Kind code of ref document: A3

Designated state(s): DE FR GB NL

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE APPLICATION IS DEEMED TO BE WITHDRAWN

18D Application deemed to be withdrawn

Effective date: 19890401

RIN1 Information on inventor provided before grant (corrected)

Inventor name: PICCO, PAOLO

Inventor name: CAVIONI, TIZIANA

Inventor name: MAURELLI, ALFONSO