EP0460840A2 - Digitalfehlerkorrektursystem für in Bereiche unterteilten Analog-Digitalwandler - Google Patents

Digitalfehlerkorrektursystem für in Bereiche unterteilten Analog-Digitalwandler Download PDF

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Publication number
EP0460840A2
EP0460840A2 EP91304721A EP91304721A EP0460840A2 EP 0460840 A2 EP0460840 A2 EP 0460840A2 EP 91304721 A EP91304721 A EP 91304721A EP 91304721 A EP91304721 A EP 91304721A EP 0460840 A2 EP0460840 A2 EP 0460840A2
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Prior art keywords
analog
signal
binary
stage
conversion
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EP91304721A
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English (en)
French (fr)
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EP0460840A3 (en
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David Byrd Ribner
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General Electric Co
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General Electric Co
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    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/06—Continuously compensating for, or preventing, undesired influence of physical parameters
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1057—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values
    • H03M1/1061—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by trimming, i.e. by individually adjusting at least part of the quantisation value generators or stages to their nominal values using digitally programmable trimming circuits
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/10—Calibration or testing
    • H03M1/1009—Calibration
    • H03M1/1033—Calibration over the full range of the converter, e.g. for correcting differential non-linearity
    • H03M1/1038—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables
    • H03M1/1042—Calibration over the full range of the converter, e.g. for correcting differential non-linearity by storing corrected or correction values in one or more digital look-up tables the look-up table containing corrected values for replacing the original digital values
    • H—ELECTRICITY
    • H03—ELECTRONIC CIRCUITRY
    • H03M—CODING; DECODING; CODE CONVERSION IN GENERAL
    • H03M1/00—Analogue/digital conversion; Digital/analogue conversion
    • H03M1/12—Analogue/digital converters
    • H03M1/14—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit
    • H03M1/16—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps
    • H03M1/164—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages
    • H03M1/167—Conversion in steps with each step involving the same or a different conversion means and delivering more than one bit with scale factor modification, i.e. by changing the amplification between the steps the steps being performed sequentially in series-connected stages all stages comprising simultaneous converters

Definitions

  • the present invention generally relates to multi-stage, pipelined subranging analog-to-digital converters and, more particularly, to a system for correcting conversion errors in multi-stage pipelined, subranging analog-to-digital converters.
  • a subranging analog-to-digital converter is described by A.G.F. Dingwall and W. Zazzu in "An 8-MHz CMOS Subranging 8-Bit A/D Converter", IEEE J. Solid-State Circuits , Vol. SC-20, pp. 1138-1143, December 1985, and S.H. Lewis and P.R. Gray in "A Pipelined 5-M Sample/s 9-Bit Analog-To-Digital Converter", IEEE J. Solid-State Circuits , Vol. SC-22, No. 6, pp. 954-961, December 1987.
  • the interstage gain is made one half of the conventional amount, i.e., 2 L-1 for a stage that uses L-bit analog-to-digital (A/D) and digital-to-analog (D/A) converters.
  • the residual signal thus spans only half of the range of the subsequent stage.
  • errors in the A/D converter of any stage up to ⁇ 1/2 of a least significant bit (LSB), can be accommodated.
  • LSB least significant bit
  • Such errors will cause the amplified residual signal to fall either above or below the expected range and can be corrected by either incrementing or decrementing the L-bit A/D converter code for the prior stage respectively.
  • this method is very simple, it cannot correct any error in the D/A converter, or in the gain stage, and it is not sufficient for high resolution (i.e., resolution above 9 bits).
  • Subranging analog-to-digital converters are attractive for high-speed operation since they are almost comparable in speed to a flash converter, but use far less hardware.
  • an N-bit flash converter makes use of 2 N - 1 comparators, while the same resolution in an L stage subranging architecture requires only L(2 N/L -1) comparators.
  • efforts to obtain high resolution are hampered by practical circuit nonidealities such as component mismatching, nonlinearity, offset, noise, etc.
  • accuracy is limited by the degree of linearity of the A/D and D/A converters in the first stage. Resolution at accuracy levels beyond the limits of the nonideal components mentioned above, however, is obtainable by use of this invention.
  • a digital error correction system facilitates calibration of the subranging analog-to-digital converter to avoid errors in the operation of the converter. High resolution analog-to-digital conversion with a subranging architecture is thereby facilitated.
  • the intent is to use digital techniques as much as possible to mitigate the effects of component mismatches and nonlinearities that otherwise limit resolution to a lower level.
  • the architecture which supports a digitally correctable A/D converter is consistent with general subranging architectures so as to be efficient in terms of required chip area and power dissipation.
  • the architecture is also amenable to pipelining for high-speed operation, and uses a limited number of digital coefficients to implement the correction of the circuit nonidealities.
  • Application of that approach is intended to enable analog-to-digital conversion to take place with accuracy levels considerably beyond the limits imposed by circuit nonidealities or impairments. It is contemplated that 16-bit resolution at conversion rates of upwards of 25 MHz, well beyond the present state of the art, can be obtained from standard integrated circuit technologies using the present invention.
  • the converter includes a plurality of conversion stages connected in cascade, each stage including a sample-and-hold circuit, an analog-to-digital converter for converting an analog input signal into a binary conversion signal which corresponds to the nearest quantized level below that of the analog input signal, a digital-to-analog converter for converting the binary conversion signal into a quantized analog signal which corresponds to the nearest quantized level below that of the analog input signal, summation means for subtracting the quantized analog signal from the analog,input signal to generate a residual analog signal, and a gain amplifier which amplifies the residual analog signal for application to the next conversion stage.
  • the binary conversion signal addresses an individual look-up table to provide a compensated binary signal which is selected to compensate for nonidealities of the converter components.
  • the compensated binary signals from the look-up tables provide a corrected output signal when combined or summed together.
  • the binary conversion signal in the stages for the most significant bits address a common look-up table, while each of the remaining stages addresses a respective individual look-up table.
  • a simple method of calibration which makes use of a least-mean-squared adaptation algorithm, is also provided.
  • This technique accommodates practical circuit nonidealities such as component mismatching, gain error and voltage offsets, and also handles high levels of amplifier nonlinearity.
  • the architecture is applicable to any subranging converter with an arbitrary number of stages and number of bits per stage.
  • FIG. 1 A block diagram of a basic subranging converter, as known in the prior art, is shown in Figure 1.
  • the converter comprises two or more similar conversion stages (1, 2,...M) connected together in a cascade arrangement.
  • Each conversion stage includes a sample-and-hold (S/H) circuit 10 to which an analog input signal is applied.
  • S/H sample-and-hold
  • Each stage uses a low resolution A/D converter 12 to generate a binary conversion signal corresponding to the nearest quantized level below that of the analog input signal applied to sample-and-hold circuit 10 of that stage, while a companion D/A converter 14 generates a quantized analog signal corresponding to the nearest quantized level below that of the analog input signal applied to the sample-and-hold circuit 10 of that stage.
  • This quantized analog signal in each stage is subtracted from the analog input signal in that stage by a summation circuit 16 which generates a residual analog signal that is less than one LSB of the digital-to-analog converter 14 in that stage.
  • a subsequent gain amplifier 18 in each stage boosts the residual signal in that stage back to a level consistent with the input range of the next stage.
  • each stage digitally approximates its analog input signal and passes the remainder of that analog signal (after amplification) on to the following stage for further processing.
  • each stage In pipelined operation, the signal processed by each stage is delayed from the preceding stage by one sample period. Thus a latency of M clock cycles is required before an output signal is available from the final stage.
  • the output signals of earlier stages are available sooner and must be delayed accordingly before being combined into a single output signal.
  • This is implemented, as shown in Figure 1, by advancing the binary conversion signal from the analog-to-digital converter 12 of each conversion stage through a plurality of stages 20 of a shift register in each conversion stage.
  • the shift register in each successive conversion stage has one less stage 20 than the shift register of the previous conversion stage, except for the final conversion stage which employs no shift register.
  • the parallel outputs from each conversion stage are combined to produce a resultant binary output signal which represents the analog input signal to the multi-stage analog-to-digital converter.
  • the architecture of multi-stage analog-to-digital converter 64 shown in Figure 2, is an improvement of the subranging architecture of Figure 1 discussed above.
  • the improved architecture comprises the basic pipelined subranging structure of Figure 1 along with individual digital look-up tables 30 for each of the conversion stages (1, 2,...M).
  • the M sets of uncorrected digital output signals D i , 1 ⁇ i ⁇ M, of the M subranging stages address the respective M look-up tables 30.
  • each look-up table 30 implements an arbitrary discrete valued nonlinear function of its digital input signal. A method to calibrate the converter, i. e., to incorporate the required coefficients into the look-up tables, is described below.
  • Each look-up table 30 can be constructed as either a read only memory (ROM) or a random access memory (RAM), depending on the desired calibration method.
  • Each look-up table 30 has a number of binary address inputs equal to the number of bits of the A/D converter 12 for its respective stage, i.e., n i binary address inputs for any stage i in Figure 2, and thus have 2 n i coefficients.
  • the binary word size of these coefficients, in any stage is greater than the total number of bits of A/D converter 12 in that stage, to facilitate correction and calibration.
  • the interstage amplifiers 18 have gains of less than what is required for a conventional subranging analog-to-digital converter.
  • the gains of the gain amplifiers 18 and sample-and-hold circuits 10 are reduced to accommodate errors in the interstage A/D and D/A converters, i.e., G i ⁇ 2 i n ; 1 ⁇ i ⁇ M
  • G i ⁇ 2 i n A practical choice of gain is that used in the digital correct ion method G i ⁇ 2 i-1 n ; 1 ⁇ i ⁇ M
  • the actual gain values chosen could be greater or less than these amounts, depending on the expected values of errors.
  • FIG. 3 A variation 64′ of the pipelined multi-stage analog-to-digital converter is shown in Figure 3 wherein like reference numerals indicate the same (or corresponding) elements as in Figure 2.
  • a single look-up table 31 is used for the most significant bits (MSBs) corresponding to D L output signals of the first L stages.
  • MSBs most significant bits
  • Separate look-up tables 30′ are used for each of the remaining stages.
  • the required number of coefficients in this implementation increases to It is desirable to keep the number of stages L connected to the first look-up table 31 as small as possible to minimize the number of coefficients.
  • the A/D converter implementation 64′ of Figure 3 uses a larger total number of digital coefficients to enable it to correct more accurately for errors due to static nonlinearities.
  • the number of stages L incorporated together as inputs to the first table in A/D converter 64′ governs the degree of nonlinearity that is correctable therein. In general, the smallest number of stages that provides acceptable nonlinearity correction should be used in order to reduce the total number of table coefficients required. Nonlinearity in subsequent stages L+1 to M are not corrected; however, their effects are attenuated by their input-referred gains as mentioned earlier.
  • Calibration can be done in various ways depending on the application. For example, a general approach that uses a least-mean-squared (LMS) adaptive algorithm is described by B. Widrow and S.D. Stearns in Adaptive Signal Processing , Prentice-Hall, 1985, pp. 99-114. Two examples, shown in Figures 4A and 4B, use an ideal (in relation to the specific application), so-called “gold standard”, converter to generate what is termed an "exact” output and use LMS adaptation of the look-up table coefficients. In actual practice, the "gold-standard", or reference, converter needs to be only one order of magnitude (or less) better in accuracy than the objective specification for the analog-to-digital converter after calibration.
  • LMS least-mean-squared
  • a 14-bit "gold-standard” converter is adequate.
  • the techniques shown in Figures 4A and 4B differ only in that a digital-to-analog converter 40 is used as the "gold standard" reference in Figure 4A whereas an analog-to-digital converter 50 is used in Figure 4B.
  • the use of the D/A converter standard is probably the most practical approach to implement since it is usually easier to make a high precision D/A converter than an A/D converter.
  • the table look-up LMS algorithm is for the A/D converter 64 of Figure 2 and for the A/D converter 64′ of Figure 3, where ⁇ n is the error after the n th iteration, and ⁇ is the convergence coefficient, usually a constant, and normally ⁇ 1.
  • Table F1(D1, D2...D L ) designates a memory block with an output selected by the concatenation of address bits D1 through D L .
  • the word size of the table coefficients should be greater than the desired number of bits to allow for ⁇ I. In this algorithm, only the coefficient from each table that was used in forming the n th output is updated at each iteration. Speed of adaptation therefore drops with respect to the size of tables that are used, i.e., the more coefficients per table, the longer it takes to converge since only one coefficient per table is adjusted on each conversion. Other adaptation algorithms may be used if appropriate.
  • a random sequence generator 48 applies a random binary signal to an ideal ("gold standard") digital-to-analog converter 40.
  • the binary signal is converted into an analog signal which is applied via a switch S1 to the input of the multi-stage analog-to-digital converter 64.
  • a digital subtractor 52 computes the difference between the binary signal from random sequence generator 48 and the binary output signal produced by summation unit 32 (shown in Figures 2 and 3) and produces an error signal ⁇ representing the difference between the binary signals.
  • the error signal ⁇ is applied to a processor (not shown) which performs an adaptation algorithm and returns a corrected coefficient to each of the look-up tables of multi-stage analog-to-digital converter 64.
  • a random signal generator 60 applies a random analog signal via a switch S1 to an ideal ("gold standard") analog-to-digital converter 50 and to the input of multi-stage analog-to-digital converter 64.
  • a digital subtractor 62 computes the difference between the binary signal produced by the "gold standard” analog-to-digital converter 50 and the binary output signal from summation unit 32 (shown in Figures 2 and 3) and produces an error signal ⁇ representing the difference between the binary signals.
  • the error signal ⁇ is applied to a processor (not shown) which performs an adaptation algorithm and returns a corrected coefficient to each of the look-up tables of multi-stage analog-to-digital converter 64. It should be noted that the foregoing description of operation of the system of Figure 4B is the same if analog-to-digital converter 64′ (of Figure 3) is substituted for analog-to-digital converter 64 (of Figure 2).
  • the A/D converters of the improved architecture operate properly and correct errors for high accuracy.
  • the A/D converters can be calibrated during manufacture and the coefficients can be stored in the correction memory of the A/D converters for later use.
  • the A/D converter itself does not require calibration hardware, thereby avoiding this complexity and the costs associated therewith, and consists only of the circuitry shown in either Figure 2 or Figure 3.
  • a system for calibrating either of these embodiments of the A/D converter during manufacture, or in applications requiring recalibration is shown in Figure 5.
  • the system includes the A/D converter 64 to be calibrated (although A/D converter 64′, shown in Figure 3, may be used instead) along with an external "gold-standard" reference A/D or D/A converter, external look-up tables (or memory blocks) and a processor.
  • the external coefficients can be programmed into a programmable ROM (PROM) or electronically erasable PROM (EEPROM) on the A/D converter chip itself.
  • PROM 30 is shown in the calibration system (or calibration fixture) of Figure 5.
  • the memory within the off-chip hardware converges to a calibrated set of coefficient values using the update algorithm, i.e., the table look-up LMS algorithm described earlier.
  • the advantage of using this technique is that the on-chip circuitry for calibration is kept to a minimum. In environments where substantial changes in circuit operating conditions due to variations in power supply levels or temperature could put a corrected A/D converter out of specification, the calibration circuitry of Figures 4(a), 4(b) or 5 must be included along with the A/D converter to permit periodic recalibration.
  • multi-stage analog-to-digital converter 64 (though analog-to-digital converter 64′ may be used in the same way instead) is placed in a calibration fixture which includes a random sequence generator 70 for supplying a random binary signal to a "gold standard" digital-to-analog converter 72 wherein the binary signal is converted into an analog signal.
  • the output analog signal from D/A converter 72 is applied via a switch S1 to the analog input of multi-stage analog-to-digital converter 64.
  • the uncorrected output signals from each stage of the multi-stage analog-to-digital converter are applied to a set of external look-up tables 74 which correspond to look-up tables 30 in the conversion stages of multi-stage analog-to-digital converter 64.
  • the external look-up tables 74 produce binary signals or coefficients which are combined by a summation unit 76 to produce a binary output signal.
  • a digital subtractor 78 computes the difference between the binary signal generated by random sequence generator 70 and the binary output signal from summation unit 76 and produces an error signal ⁇ representing the difference between the latter two binary signals. Error signal ⁇ is applied to a processor 80, or to a finite state machine (not shown), which performs an update algorithm to correct the coefficients in look-up tables 74 until error signal ⁇ is reduced to a level close to zero.
  • the coefficients stored in external look-up tables 74 are stored in the internal look-up tables 30 of multi-stage analog-to-digital converter 64.
  • the calibration fixture of Figure 5 can employ a random analog signal generator and a "gold standard" analog-to-digital converter arranged as shown in Figure 4B for calibration of multi-stage analog-to-digital converter 64.
  • analog-to-digital converter 64′ shown in Figure 3, may be used in the calibration system of Figure 5 in the same manner as analog-to-digital converter 64.
  • the calibration circuitry can alternatively be incorporated on-chip.
  • An oversampled D/A or A/D converter operated at a reduced conversion rate or other high precision D/A or A/D converter can be used as the "gold standard" reference.
  • Other variations in implementation are possible and within the scope of this invention, including a configuration whereby the correction coefficients are stored externally and loaded into internal RAM after calibration.
  • Another configuration within the scope of this invention employs a separate digital system or chip to implement the correction using PROM or RAM along with a processor or a finite state machine.
  • This invention also encompasses discrete (i.e., circuit board level) implementations, in addition to the integrated circuit oriented approaches described herein.
  • the logic of the calibration process is shown in the flow chart of Figure 6 for the A/D converter 64 of Figure 2.
  • the process described is for the calibration system illustrated in Figure 4A.
  • the process starts by resetting an n register in multi-stage A/D converter 64 at step 90. This is a register that keeps track of the number of calibration cycles performed.
  • a voltage V in is then generated by first inputting a random number to "gold standard" D/A converter 40 from random sequence generator 48 at step 92, and this random number is supplied by D/A converter 40 to A/D converter 64 at step 94.
  • the analog-to-digital process is initiated at step 96.
  • the 1 register is set to 1 at step 106.
  • the error ⁇ in the converted output signal is determined as the difference between V in and V A/D by subtractor 52 (shown in Figure 4A) or subtractor 78 (shown in Figure 5).
  • the corrected coefficient for the 1 th table is generated at step 110 as the sum of the output signal of the 1 th table for an input address of D1 and a change in the error, ⁇ , and the 1 register is then incremented by one at step 112. This process continues until 1 is greater than n stages , the number of stages of the pipelined A/D converter, as determined at step 114. At this point, the n register is incremented by one at step 116.
  • a test is next made at step 118 to determine if the content of the n register is greater than the number of calibration cycles. If not, the process loops back to step 92 and the process repeats. When the n register content exceeds the number of calibration cycles, the calibration process is complete.
  • the A/D converter is being calibrated. If calibration is being performed during manufacture using external hardware, as shown in Figure 5, then the calibration coefficients must subsequently be programmed into the internal look-up tables of the A/D converter 64 (or 64′). If the calibration hardware is incorporated in a system together with the A/D converter itself, then the next step is to transfer coefficients to internal A/D converter look-up tables if external tables were used. Once this is done, in either situation, the A/D converter is ready for normal signal conversion operation.

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  • Physics & Mathematics (AREA)
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  • Analogue/Digital Conversion (AREA)
EP19910304721 1990-06-04 1991-05-24 Digital error correction system for subranging analog-to-digital converters Withdrawn EP0460840A3 (en)

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US07/533,263 US5047772A (en) 1990-06-04 1990-06-04 Digital error correction system for subranging analog-to-digital converters
US533263 1990-06-04

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EP0460840A2 true EP0460840A2 (de) 1991-12-11
EP0460840A3 EP0460840A3 (en) 1993-10-20

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EP (1) EP0460840A3 (de)
JP (1) JPH0583134A (de)
KR (1) KR940005935B1 (de)
CN (1) CN1057136A (de)
CA (1) CA2042142A1 (de)
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KR920001859A (ko) 1992-01-30
IL98220A0 (en) 1992-06-21
JPH0583134A (ja) 1993-04-02
KR940005935B1 (ko) 1994-06-24
US5047772A (en) 1991-09-10
EP0460840A3 (en) 1993-10-20
CA2042142A1 (en) 1991-12-05

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