EP1103031A1 - Composant semi-conducteur presentant une passivation - Google Patents

Composant semi-conducteur presentant une passivation

Info

Publication number
EP1103031A1
EP1103031A1 EP99945847A EP99945847A EP1103031A1 EP 1103031 A1 EP1103031 A1 EP 1103031A1 EP 99945847 A EP99945847 A EP 99945847A EP 99945847 A EP99945847 A EP 99945847A EP 1103031 A1 EP1103031 A1 EP 1103031A1
Authority
EP
European Patent Office
Prior art keywords
passivation
layer
layers
double
structured
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP99945847A
Other languages
German (de)
English (en)
Inventor
Josef Willer
Paul-Werner Von Basse
Thomas Scheiter
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of EP1103031A1 publication Critical patent/EP1103031A1/fr
Withdrawn legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06V—IMAGE OR VIDEO RECOGNITION OR UNDERSTANDING
    • G06V40/00—Recognition of biometric, human-related or animal-related patterns in image or video data
    • G06V40/10—Human or animal bodies, e.g. vehicle occupants or pedestrians; Body parts, e.g. hands
    • G06V40/12—Fingerprints or palmprints
    • G06V40/13—Sensors therefor
    • G06V40/1306—Sensors therefor non-optical, e.g. ultrasonic or capacitive sensing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H10W74/10—Encapsulations, e.g. protective coatings characterised by their shape or disposition
    • H10W74/131—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed
    • H10W74/147—Encapsulations, e.g. protective coatings characterised by their shape or disposition the semiconductor body being only partially enclosed the encapsulations being multilayered

Definitions

  • Passivation double layer e.g. B. again an oxide, deposited somewhat thicker.
  • the latter layer 8 is removed somewhat, e.g. can be done by means of CMP (chemical mechanical polishing). Alternatively or in addition, an etching process can be used. This results in a very flat surface of this layer 8.

Landscapes

  • Engineering & Computer Science (AREA)
  • Human Computer Interaction (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Multimedia (AREA)
  • Theoretical Computer Science (AREA)
  • Formation Of Insulating Films (AREA)
  • Measurement Of The Respiration, Hearing Ability, Form, And Blood Characteristics Of Living Organisms (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Image Input (AREA)
  • Measurement Of Length, Angles, Or The Like Using Electric Or Magnetic Means (AREA)
  • Investigating Or Analyzing Materials By The Use Of Electric Means (AREA)
  • Investigating Or Analyzing Materials By The Use Of Fluid Adsorption Or Reactions (AREA)

Abstract

L'invention concerne un composant présentant une passivation constituée d'au moins deux doubles couches de passivation, dont la couche supérieure est appliquée sur une surface plane de la couche se trouvant en-dessous. Les doubles couches de passivation sont constituées de deux couches en matériaux diélectriques différents, par exemple de l'oxyde de silicium et du nitrure de silicium. Les épaisseurs respectives des couches de passivation individuelles peuvent être adaptées aux dimensions de la structuration de la couche sur laquelle est appliquée la passivation. On obtient ainsi une passivation fiable qui est particulièrement adaptée à des capteurs d'empreintes digitales à mesure capacitive.
EP99945847A 1998-07-09 1999-07-01 Composant semi-conducteur presentant une passivation Withdrawn EP1103031A1 (fr)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
DE19830832 1998-07-09
DE19830832 1998-07-09
PCT/DE1999/001982 WO2000003345A1 (fr) 1998-07-09 1999-07-01 Composant semi-conducteur presentant une passivation

Publications (1)

Publication Number Publication Date
EP1103031A1 true EP1103031A1 (fr) 2001-05-30

Family

ID=7873546

Family Applications (1)

Application Number Title Priority Date Filing Date
EP99945847A Withdrawn EP1103031A1 (fr) 1998-07-09 1999-07-01 Composant semi-conducteur presentant une passivation

Country Status (9)

Country Link
US (1) US6664612B2 (fr)
EP (1) EP1103031A1 (fr)
JP (1) JP3527708B2 (fr)
KR (1) KR100413860B1 (fr)
CN (1) CN1135493C (fr)
BR (1) BR9911980A (fr)
RU (1) RU2195048C2 (fr)
UA (1) UA46173C2 (fr)
WO (1) WO2000003345A1 (fr)

Families Citing this family (25)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8178435B2 (en) 1998-12-21 2012-05-15 Megica Corporation High performance system-on-chip inductor using post passivation process
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
US6303423B1 (en) 1998-12-21 2001-10-16 Megic Corporation Method for forming high performance system-on-chip using post passivation process
US8421158B2 (en) 1998-12-21 2013-04-16 Megica Corporation Chip structure with a passive device and method for forming the same
US6440814B1 (en) * 1998-12-30 2002-08-27 Stmicroelectronics, Inc. Electrostatic discharge protection for sensors
US6603192B2 (en) 1999-07-30 2003-08-05 Stmicroelectronics, Inc. Scratch resistance improvement by filling metal gaps
EP1146471B1 (fr) 2000-04-14 2005-11-23 Infineon Technologies AG Capteur biométrique capacitif
US6759275B1 (en) 2001-09-04 2004-07-06 Megic Corporation Method for making high-performance RF integrated circuits
KR100449249B1 (ko) * 2001-12-26 2004-09-18 주식회사 하이닉스반도체 지문 인식 소자의 제조 방법
KR20040012294A (ko) * 2002-08-02 2004-02-11 삼성에스디아이 주식회사 지문 인식 센서를 구비한 터치 패널 장치
US7355282B2 (en) 2004-09-09 2008-04-08 Megica Corporation Post passivation interconnection process and structures
US8008775B2 (en) 2004-09-09 2011-08-30 Megica Corporation Post passivation interconnection structures
US8384189B2 (en) 2005-03-29 2013-02-26 Megica Corporation High performance system-on-chip using post passivation process
CN1901162B (zh) 2005-07-22 2011-04-20 米辑电子股份有限公司 连续电镀制作线路组件的方法及线路组件结构
JP5098276B2 (ja) * 2006-09-29 2012-12-12 富士通セミコンダクター株式会社 半導体装置の製造方法
JP4833031B2 (ja) * 2006-11-06 2011-12-07 富士通セミコンダクター株式会社 表面形状センサとその製造方法
US8749021B2 (en) 2006-12-26 2014-06-10 Megit Acquisition Corp. Voltage regulator integrated with semiconductor chip
CN101663558B (zh) * 2007-04-05 2011-06-22 富士通半导体股份有限公司 表面形状传感器及其制造方法
CN100594591C (zh) * 2007-10-17 2010-03-17 中国科学院微电子研究所 一种提高氮化镓基场效应晶体管性能的方法
WO2010075447A1 (fr) 2008-12-26 2010-07-01 Megica Corporation Boîtiers de puces munis de circuits intégrés de gestion d'énergie et techniques associées
US9812338B2 (en) 2013-03-14 2017-11-07 Cree, Inc. Encapsulation of advanced devices using novel PECVD and ALD schemes
US8994073B2 (en) 2012-10-04 2015-03-31 Cree, Inc. Hydrogen mitigation schemes in the passivation of advanced devices
US9991399B2 (en) 2012-10-04 2018-06-05 Cree, Inc. Passivation structure for semiconductor devices
CN104201115A (zh) * 2014-09-12 2014-12-10 苏州晶方半导体科技股份有限公司 晶圆级指纹识别芯片封装结构及封装方法
CN106904568B (zh) * 2015-12-23 2019-06-28 中芯国际集成电路制造(上海)有限公司 一种mems器件及其制备方法、电子装置

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6471172A (en) * 1987-09-11 1989-03-16 Oki Electric Ind Co Ltd Complete contact type image sensor
JPH01207932A (ja) 1988-02-16 1989-08-21 Fuji Electric Co Ltd 半導体装置
JPH04109623A (ja) * 1990-08-29 1992-04-10 Nec Corp ｐｎ接合を有する半導体装置
JPH04184932A (ja) * 1990-11-20 1992-07-01 Sony Corp パッシベーション膜の形成方法
JPH0590255A (ja) * 1991-09-30 1993-04-09 Sanyo Electric Co Ltd 半導体装置
RU2024992C1 (ru) * 1992-06-11 1994-12-15 Научно-исследовательский институт молекулярной электроники Способ планаризации интегральных схем
DE4236133C1 (de) * 1992-10-26 1994-03-10 Siemens Ag Sensoranordnung zur Erfassung von Fingerabdrücken und Verfahren zu deren Herstellung
JPH08148485A (ja) * 1994-11-15 1996-06-07 Fujitsu Ltd 半導体装置の製造方法
FR2739977B1 (fr) * 1995-10-17 1998-01-23 France Telecom Capteur monolithique d'empreintes digitales
US5851603A (en) * 1997-07-14 1998-12-22 Vanguard International Semiconductor Corporation Method for making a plasma-enhanced chemical vapor deposited SiO2 Si3 N4 multilayer passivation layer for semiconductor applications
US6240199B1 (en) * 1997-07-24 2001-05-29 Agere Systems Guardian Corp. Electronic apparatus having improved scratch and mechanical resistance
US6028773A (en) * 1997-11-14 2000-02-22 Stmicroelectronics, Inc. Packaging for silicon sensors
US6091132A (en) * 1997-12-19 2000-07-18 Stmicroelectronics, Inc. Passivation for integrated circuit sensors
US6091082A (en) * 1998-02-17 2000-07-18 Stmicroelectronics, Inc. Electrostatic discharge protection for integrated circuit sensor passivation
US6097195A (en) * 1998-06-02 2000-08-01 Lucent Technologies Inc. Methods and apparatus for increasing metal density in an integrated circuit while also reducing parasitic capacitance

Also Published As

Publication number Publication date
RU2195048C2 (ru) 2002-12-20
JP3527708B2 (ja) 2004-05-17
CN1308751A (zh) 2001-08-15
UA46173C2 (uk) 2002-05-15
WO2000003345A1 (fr) 2000-01-20
JP2002520841A (ja) 2002-07-09
KR100413860B1 (ko) 2004-01-07
RU2001103636A (ru) 2004-03-20
KR20010071808A (ko) 2001-07-31
US20010019168A1 (en) 2001-09-06
BR9911980A (pt) 2001-03-27
CN1135493C (zh) 2004-01-21
US6664612B2 (en) 2003-12-16

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