Classifications

• • G—PHYSICS
  • G04—HOROLOGY
  • G04G—ELECTRONIC TIME-PIECES
  • G04G99/00—Subject matter not provided for in other groups of this subclass
• • G—PHYSICS
  • G04—HOROLOGY
  • G04G—ELECTRONIC TIME-PIECES
  • G04G3/00—Producing timing pulses
  • G04G3/02—Circuits for deriving low frequency timing pulses from pulses of higher frequency

Definitions

• the present invention relates to an electronic timepiece allowing the display of several time indications. More particularly, the present invention relates to a timepiece allowing the display of at least a first and a second time indication, the first time indication being based on the Hour-Minute-Second system (hereinafter HMS) .
• HMS Hour-Minute-Second system
• timepieces allowing the display of a plurality of time indications.
• These timepieces commonly known as “universal timepieces” are typically provided to allow the display of a time indication representative of universal time and one or more time indications representative of local time corresponding to different time zones.
• This multitude of time indications can generate risks of confusion for the user when they are read and generally requires that means be provided making it possible to clearly identify what each of the time indications displayed relates to.
• An object of the present invention is thus to propose an electronic timepiece allowing the display of at least a first and a second time indication, and by means of which the user can not clearly and quickly identify and differentiate the time indications. displayed.
• the present invention relates to an electronic timepiece allowing the display of at least a first and a second time indication, said first time indication being based on the Hour-Minute-Second system, this piece of timepiece comprising a time base delivering pulses to a frequency divider circuit comprising N binary division stages and delivering first control pulses making it possible to form and display said first time indication, this timepiece being characterized in that said second time indication is based on a decimal system in which time is divided at least into thousandths of a day, this timepiece further comprising generation means adapted to deliver, from auxiliary control pulses from said base of time, second control pulses making it possible to form and display said second time indication.
• the solution recommended by the present invention thus makes it possible to clearly differentiate the first time indication from the second by the fact that the first and second time indications are based on different systems.
• the conventionally used H-M-S system consists in dividing the day into 24 hours, 1 hour being divided into 60 minutes, and 1 minute into 60 seconds.
• a division of time based on the decimal system consists in return of dividing the day, no longer according to the conventional scheme mentioned above, but successively, in tenths of a day (equivalent to 2.4 hours or 144 minutes), themselves divided into hundredths of a day (equivalent to 14.4 minutes or 864 seconds), then in thousandths of a day (equivalent to 86.4 seconds), etc.
• the second time indication requires only three digits ("000" to "999") to be displayed and is thus clearly distinguished from a conventional time indication based on the system.
• HMS typically displayed in "HH: MM” format. The risks of confusion when reading the time indications are thus greatly reduced.
• the atypical format of the second time indication is for example particularly suitable for displaying a universal time to which the user can clearly refer without confusing it with a conventional time indication relating to the time zone in which he is located.
• the decimal system is also an interesting alternative to the H-M-S system conventionally in force because it eliminates the conversion problems inherent in the H-M-S format. This alternative is moreover more logical and comprehensible for the already customary user of the decimal system.
• electronic timepieces commonly comprise a time base, typically a quartz oscillator delivering pulses at a determined frequency equivalent to a binary power, for example 32768 Hz.
• a circuit frequency divider composed of a succession of N binary division stages (flip-flops) connected in cascade, is coupled to the time base so as to deliver control pulses whose frequency is reduced by a factor of 2.
• these control pulses are thus used to control the respective displays of these time indications.
• control pulses making it possible to form a time indication based on a decimal system in which time is divided at least into thousandths of a day
• it will be chosen to generate the second control pulses either at a frequency of 1 / 86.4 Hz or at a frequency of 1 / 8.64 Hz, higher frequencies can nevertheless be chosen depending on the case.
• a trivial solution to this problem consists in providing an additional time base making it possible to deliver pulses at a specific frequency corresponding to a multiple of the desired frequency, for example 10O00 Hz.
• a frequency divider circuit having for example an equivalent division ratio at 86,400 would thus generate control pulses at a frequency of 1 / 8.64 Hz.
• This trivial solution thus involves the use of two chains of distinct divisions (time base + frequency divider circuit) to display the first and second time indications.
• the timepiece is advantageously adapted to derive the control pulses from the first and second time indications from the same time base.
• it includes generation means adapted to deliver, from auxiliary control pulses originating from the time base, the second control pulses making it possible to form and display the second time indication.
• the timepiece can thus be particularly adapted to derive, from pulses at 1 Hz from the time base at the output of the frequency divider circuit, second control pulses having a frequency of 1 / 86.4 Hz so to form a second hourly indication to the thousandth of a day, and this despite the fact that the division ratio of these frequencies is not whole.
• Another advantage of the present invention thus lies in the fact that a single time base is used to generate the different control pulses of the first and second time indications and that it is consequently possible to adapt the electronics of a conventional timepiece so that it allows the display of a time indication based on the decimal system.
• FIG. 1 shows a simplified block diagram of a timepiece constituting a first embodiment of the present invention
• FIG. 2 shows a simplified block diagram of a timepiece constituting a second embodiment of the present invention
• FIG. 3a and 3b show plan views of timepieces according to the present invention illustrating different possibilities of displaying time indications
• FIG. 4 shows a flowchart of implementation of a first alternative embodiment of the generation means for delivering the control pulses for the display of the time indication based on the decimal system
• - Figure 5 shows a second alternative embodiment of the generation means for delivering the control pulses for the display of the time indication based on the decimal system
• - Figures 5a to 5c show examples of application of the second alternative embodiment of the generation means 14 illustrated in Figure 5;
• FIG. 6 shows a third alternative embodiment of the generation means for delivering the control pulses for the display of the time indication based on the decimal system
• FIG. 6a presents an example of application of the third alternative embodiment of the generation means 14 illustrated in FIG. 6.
• FIG. 1 there is shown in Figure 1, in the form of a simplified block diagram, a timepiece constituting a first embodiment of the present invention.
• This timepiece includes in series a time base 2, typically formed of a quartz oscillator, a frequency divider circuit 4 comprising N binary division stages 4.1 to 4.N and delivering first control pulses l 1 f and first display means 6 controlled by the first control pulses l
• the above-mentioned numerical values will be used as an example.
• the first display means 6 are controlled by the first control pulses ⁇ and are arranged in a conventional manner so that they allow the formation and display of a first time indication H-, based on the H-M-S system.
• the timepiece according to the present invention further comprises generation means 14 delivering second control pulses l 2 whose frequency is determined by the decimal division adopted, that is for example 1 / 86.4 Hz in the case where a division into thousandths of a day is adopted.
• These generation means 14 are controlled by auxiliary control pulses l L from the time base 2 and delivered, in this embodiment, at the output of one of the binary division stages 4.1 to 4.N of the circuit frequency divider 4, this stage being indicated by the reference 4.L and being able to be chosen from the set of binary division stages 4.1 to 4.N.
• the frequency of the auxiliary control pulses l L is equivalent to the frequency of the pulses delivered by the time base 2 reduced by a factor 2 L.
• Variant embodiments of the generation means 14 will be presented in more detail in the remainder of this description.
• second display means 16 are connected. These second display means 16 are controlled by the second control pulses l 2 and are arranged so that they allow training and display of a second time indication H 2 based on the decimal system.
• FIG. 2 there is shown in Figure 2, in the form of a simplified block diagram, a timepiece constituting a second embodiment of the present invention.
• This timepiece comprises in series, the time base 2, the frequency divider circuit 4, the first and second display means 6 and 16, as well as the means 14 for generating second control pulses l 2 .
• This timepiece further comprises N * additional binary division stages 4.N + 1 to 4.N + N * connected following the frequency divider circuit 4.
• the generation means 14 are controlled by auxiliary pulses of command l L also issued from time base 2 and delivered, in this embodiment, at the output of the additional binary division stages 4.N + 1 to 4.N + N * .
• the frequency of the auxiliary control pulses l L is equivalent, in this case, to the frequency of the pulses delivered by the time base 2 reduced by a factor 2 N + N * .
• FIGS. 1 and 2 thus allow the display of a first time indication H 1 based on the HMS system, and of a second time indication H 2 based on the decimal system.
• the second control pulses l 2 are thus generated from auxiliary control pulses l L coming from time base 2.
• the timepiece according to the present invention further comprises correction means allowing the adjustment of the different time indications.
• correction means have not been described here and are not shown in FIGS. 1 and 2. Those skilled in the art will nonetheless know how to make these correction means so that they make it possible to adjust each time indication adequately.
• the embodiments shown in Figures 1 and 2 are not limiting.
• additional display means can also be provided so as to allow the training and display of additional time indications based on the HMS system or the decimal system.
• FIGS. 3a and 3b show plan views of timepieces according to the present invention illustrating different possibilities for displaying the time indications H ⁇ and H 2 .
• the first display means 6 of the first time indication H 1 can be produced in the form of a digital display allowing, for example, the display of the time indication ⁇ according to a conventional format "HH: MM".
• these first display means can for example comprise, as shown in FIG. 3b, first and second hands driven by electromechanical means (not shown) and allowing the display of the hours and the minutes respectively.
• the second display means 16 of the second time indication H 2 are advantageously formed, as illustrated in FIGS. 3a and 3b, of a digital display comprising, in this example, 3 digits so as to allow the display of the second time indication H 2 in thousandths of a day.
• These second display means 16 can however also be produced in the form of an analog display with needles driven by electromechanical means in a similar manner to the first display means 6 illustrated in FIG. 3b.
• the generation means 14 for delivering the second control pulses l 2 will now be described with the aid of Figures 4 to 6 different alternative embodiments of the generation means 14 for delivering the second control pulses l 2 according to the present invention.
• the second control pulses l 2 must be delivered at a frequency of 1 /86.4 Hz or 1 / 8.64 Hz respectively.
• the auxiliary control pulses l L are used, according to the present invention, to generate the second control pulses l 2 .
• the frequency of the auxiliary control pulses l L is determined by the binary division stage at the output of which these are delivered. According to the first embodiment described in FIG. 1, this frequency thus equals the frequency of the pulses delivered by the time base 2 reduced by a factor 2 L. According to the second embodiment described in FIG. 2, this frequency is equivalent to the frequency of the pulses delivered by the time base 2 reduced by a factor 2 N + N.
• the ratio of division of the frequency of the auxiliary control pulses L by the frequency of the second control pulses l 2 defines a numerical value corresponding to the average number of auxiliary control pulses l L to be counted to generate a control pulse l 2 . Since the frequency of the pulses delivered by the time base 2 is typically equivalent to a binary power, the division ratio defines a non-integer numerical value due to the decimal division of the day. It will be noted that it is not possible to count a non-integer number of auxiliary control pulses l L. Consequently, in the context of the present invention, the integers n and n + 1 are respectively defined directly below and above the aforementioned division ratio. These integers n and n + 1 thus correspond respectively to the integers directly lower and greater than the average number of auxiliary control pulses l L to be counted to generate a control pulse l 2 .
• the second control pulses l 2 are generated at an average frequency corresponding to the desired frequency, for example 1 / 86.4 Hz or 1 / 8.64 Hz, n and n + 1 auxiliary control pulses l L are thus successively counted according to a determined counting sequence.
• This counting sequence is formed by a succession of counting operations of n and n + 1 auxiliary control pulses l L.
• the division ratio defined above determines the period as well as the number of counting operations at the end of which the second control pulses 12 are generated at the desired average frequency.
• This counting sequence is further preferably formed so that the deviations generated during the counting sequence are minimized.
• the frequency division ratio is equivalent to 86.4.
• the division ratio further defines that 5 control pulses l 2 must be generated during a period of 432 seconds.
• the counting sequence repeated 200 times over a period of 24 hours, is thus formed of a succession of 5 counting operations.
• the 5 control pulses l 2 are preferably generated according to the following counting sequence:
• the maximum deviation generated during the counting sequence is thus limited to +/- 0.4 seconds, i.e. of the order of 0.5% of the period of the second control pulses l 2 .
• the frequency division ratio is equivalent to 10.8.
• the division ratio further defines that 5 control pulses l 2 must be generated during a period of 432 seconds. In this case, the counting sequence, repeated 200 times over a period of 24 hours, is thus formed of a succession of 5 counting operations.
• the 5 control pulses l 2 are preferably generated according to the following counting sequence:
• the maximum deviation generated during the counting sequence is thus limited to +/- 3.2 seconds, i.e. of the order of 4% of the period of the second control pulses l 2 .
• the frequency division ratio is equivalent to 8.64.
• the division ratio further defines that 25 control pulses 12 must be generated over a period of 216 seconds. In this case, the counting sequence, repeated 400 times over a period of 24 hours, is thus formed of a succession of 25 counting operations.
• the 25 control pulses 12 are preferably generated according to the following counting sequence: 9-8-9-9-8-9-8 -9-9-8-9-9-8-9-9-8-9-8-9-9-8-9-9-8-9-8-9-8-9-8-9-8-9-8-9-9-8-9.
• the maximum deviation generated during the counting sequence is thus limited to +/- 0.48 seconds, ie of the order of 5.5% of the period of the second control pulses l 2 .
• auxiliary control pulses l L determines on the one hand the precision with which the second control pulses l 2 are generated, and on the other hand the size of the registers / counters necessary for counting of auxiliary control pulses l L.
• FIG. 4 presents a flowchart for implementing the generation means 14 constituting a first alternative embodiment according to the present invention.
• these generation means 14 can advantageously be produced in the form of an integrated circuit comprising a programmed microprocessor.
• Those skilled in the art will be able, from the indications provided here, to carry out the programming of the microprocessor, so as to make it execute the functions described.
• the counting sequence begins at the block indicated by the reference 400.
• a counter register COMPT is incremented at each auxiliary control pulse l L.
• This counter register COMPT comprises a number of bits sufficient to allow the counting of at least n + 1 auxiliary control pulses l L.
• this counter register COMPT comprises at least 7 bits.
• a first test is performed at block 404 so as to check whether the value of the counter register COMPT has reached the value n.
• the counter register COMPT is incremented at block 402 at each auxiliary control pulse l L as long as the value of the latter is less than the value n, this being indicated by the affirmative output of test block 404.
• a second test is then carried out at block 406 so as to check whether the value of the counter register COMPT has exceeded the value n.
• the negative output of test block 406 leads to the third test indicated in block 408.
• it is checked, according to the counting sequence, whether the counter register COMPT must be stopped at the value n. If necessary, a control pulse l 2 is generated at block 410, ie after the counting of n auxiliary control pulses l L. Otherwise, the counter register COMPT is incremented in block 402 and, following the affirmative result of the test executed in block 406, the control pulse l 2 is then generated in block 410, ie after the counting of n + 1 pulses control auxiliaries
• the counter register COMPT is initialized in block 412 and the process begins again in block 400.
• a table representative of the counting sequence and consequently comprising as many entries as there are counting operations.
• this table includes binary values representative of the counting operation to be performed, either for example the binary value "0" if it is necessary to count n auxiliary control pulses l L or the binary value "1" whether to count n + 1 auxiliary control pulses l L.
• a binary word comprising as many bits as counting operations easily makes it possible to produce the table representative of the counting sequence.
• the use of a table representative of the counting sequence is not necessary in all cases. As will be seen below with the aid of various exemplary embodiments, certain alternatives and simplifications may indeed be envisaged.
• the register containing the value of the second hourly indication H 2 being displayed makes it possible to define an indexing value of the various entries of the table by a simple calculation of the modulo.
• Modulo obviously means the arithmetic operation giving the remainder of a division by a determined number.
• the counting sequence is preferably determined so that 5 control pulses l 2 are generated according to the following counting sequence: 86-87- 86-87-86
• This counting sequence can thus be represented by a table with 5 entries, preferably produced using the following 5-bit binary word:
• test carried out in block 408 is thus carried out by searching for the corresponding value in the table.
• a register containing the value of the second time indication H 2 being displayed, or at least the value (0 to 9) of the thousandths of days displayed will be used.
• a modulo-5 operation on the value of this register thus makes it possible to obtain an indexing value (0 to 4) of the table.
• n + 1 auxiliary control pulses l L it is determined whether to count n + 1 auxiliary control pulses l L by checking whether this result is odd.
• the counting sequence is preferably determined so that 5 control pulses l 2 are generated according to the following counting sequence:
• This counting sequence can thus be represented by a table with 5 entries, preferably produced using the following 5-bit binary word:
• a register containing the value of the thousandths of days displayed will preferably be used, in order to obtain by an operation of modulo-5 an indexing value (0 to 4) of the table.
• the counting sequence is preferably determined so that 25 control pulses l 2 are generated according to the following counting sequence:
• This counting sequence can thus be represented by a table with 25 entries, preferably produced using the following 25-bit binary word: "1 0 1 1 0 1 0 1 1 0 1 1 0 1 1 0 1 1 0 1 0 1 0 1 1 0 1 0 1 0 1 "
• test carried out in block 408 is thus carried out by searching for the corresponding value in this table.
• a register containing at least the value (0 to 99) of the thousandths and ten-thousandths of days displayed will be used.
• a modulating operation on the value of this register thus makes it possible to obtain an indexing value (0 to 24) of the table.
• FIG. 5 illustrates a second alternative embodiment of the generation means 14 making it possible to deliver the second control pulses l 2 .
• these generation means 14 comprise a primary counter 141 arranged to count n auxiliary control pulses l L , and means 142 for inhibiting the primary counter 141.
• the inhibition means 142 are controlled by the auxiliary control pulses l L and are located upstream of the primary counter 141 so as to periodically inhibit a determined number of auxiliary control pulses l L at the input of the latter.
• the second control pulses l 2 are delivered to the output of the primary counter 141.
• the inhibition means 142 preferably comprise a secondary counter 144 arranged to count m auxiliary control pulses l L , a detection logic circuit 146 coupled to the different stages of the secondary counter 144 so as to detect k intermediate states of the latter (chosen from states 0 to m-1) during which the auxiliary control pulses l L are inhibited, as well as an AND logic gate, indicated by the reference 148, comprising 2 inputs, one being inverted and connected to the output of the logic detection circuit 146 and the other receiving the auxiliary control pulses l L.
• the inhibition means 142 thus make it possible to periodically inhibit, that is to say during a period when m pulses l L are delivered, k auxiliary control pulses l L upstream of the primary counter 141.
• the logic detection circuit 146 When one of the k intermediate states is detected by the logic detection circuit 146, the latter thus sends back an inhibition signal blocking the output of the logic gate AND for the duration of an auxiliary control pulse l L so that the primary counter 141 does not "see” this pulse and does not count it.
• the k intermediate states will be chosen so that they are equidistant from each other, this so as to minimize the deviations generated.
• FIG. 5a a first example of the second variant of embodiment presented in FIG. 5 has been illustrated, applied in the case where the second control pulses l 2 are generated at an average frequency of 1 / 86.4 Hz from of auxiliary control pulses l L having a frequency of 1 Hz, ie in the case where the generation means 14 are connected to the output of the last binary division stage 4.N of the frequency divider circuit 4 (in accordance with the first mode shown in Figure 1). It will be recalled that the division ratio between the frequency of the auxiliary control pulses l L and the frequency of the second control pulses is equivalent in this case to 86.4.
• auxiliary pulses of command L L must be inhibited during the period (432 seconds) when 432 auxiliary pulses of command L L are delivered, that is, for simplicity, 1 pulse out of 216.
• the primary counter 141 thus "sees" only 430 pulses.
• control pulses l 2 are thus delivered to the output of the primary counter 141 during a period of 432 seconds, ie at the average frequency of 1 / 86.4 Hz.
• the counter by 86 can easily be achieved by means of a 7-bit binary counter arranged to be initialized after 86 impulses.
• the counter by 216 requires an 8-bit counter arranged so as to be initialized after 216 pulses.
• the primary counter 141 only "sees" 50 pulses. 5 control pulses l 2 are thus delivered to the output of the primary counter 141 during a period of 432 seconds, ie at the average frequency of 1 / 86.4 Hz.
• the counters by 10 and by 27 thus require counters 4 and 5 bits respectively.
• FIG. 5c a third example of the second alternative embodiment presented in FIG. 5 has been illustrated, applied in the case where the second control pulses l 2 are generated at an average frequency of 1 / 8.64 Hz, ie 25 pulses during a period of 216 seconds, from auxiliary control pulses l L having a frequency of 1 Hz, that is to say in the case where the generation means 14 are connected to the output of the last stage of binary division 4 .N of the frequency divider circuit 4 (in accordance with the first embodiment presented in FIG. 1). It will be recalled that the division ratio between the frequency of the auxiliary control pulses l L and the frequency of the second control pulses in this case is equivalent to 8.64.
• auxiliary pulses of command L L must be inhibited during the period (216 seconds) when 216 auxiliary pulses of command L L are delivered, that is, for simplicity, 2 pulses out of 27.
• the primary counter 141 only "sees" 200 pulses.
• 25 control pulses l 2 are thus delivered to the output of the primary counter 141 during a period of 216 seconds, that is to say at the average frequency of 1 / 8.64 Hz.
• the counters by 8 and by 27 thus require counters 3 and 5 bits respectively.
• the frequency of the auxiliary control pulses l L defines the precision at which the second control pulses l 2 are delivered.
• the higher the frequency of the auxiliary control pulses l L the greater the precision at which the second control pulses l 2 are delivered.
• this in return involves the use of counters comprising a large number of stages.
• FIG. 6 illustrates a third alternative embodiment of the generation means 14 making it possible to deliver the second control pulses l 2 . As shown in Figure 6, these generation means
• the 14 include a primary counter 241 arranged to count n + 1 auxiliary control pulses l L , and initialization means 242 ′ coupled to the primary counter 241.
• the second control pulses 12 are delivered to the output of the primary counter 241 and are used to control the initialization means 242 so as to periodically initialize the primary counter 241 with a value k corresponding to a complementary number of auxiliary pulses of command l L.
• the initialization means 242 preferably comprise a secondary counter 244 arranged to count m second control pulses l 2 and an initialization circuit 246 coupled to the different stages of the primary counter 241 so as to periodically initialize the latter, that is to say 5 say after m pulses l 2 have been delivered, with a value k corresponding to the additional number of auxiliary control pulses l L necessary for the primary counter 241 to deliver the second control pulses l 2 at the appropriate average frequency.
• the primary counter 241 is initialized with a value k so as to compensate for the missing auxiliary control pulses l L.
• FIG. 6a an example of the third variant presented in FIG. 6 has been illustrated, applied in the case where the second control pulses l 2 are generated at an average frequency of 1 / 86.4 Hz to 1 5 from auxiliary control pulses l L having a frequency of 1 Hz, ie in the case where the generation means 14 are connected to the output of the last binary division stage 4.N (4.15) of the frequency divider circuit 4 (in accordance with first embodiment presented in FIG. 1).
• control pulses l 2 are thus delivered to the output of the primary counter 241 during a period of 432 seconds, that is to say at the average frequency of 1 / 86.4 Hz.
• the counters par 87 and par 5 require counters 7 and 3 bits respectively.

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• Measuring Frequencies, Analyzing Spectra (AREA)
• Measurement Of Unknown Time Intervals (AREA)

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