EP1807761A1 - Procede et dispositif pour repartir des donnees d'au moins une source de donnees dans un systeme a plusieurs processeurs - Google Patents

Procede et dispositif pour repartir des donnees d'au moins une source de donnees dans un systeme a plusieurs processeurs

Info

Publication number
EP1807761A1
EP1807761A1 EP05801268A EP05801268A EP1807761A1 EP 1807761 A1 EP1807761 A1 EP 1807761A1 EP 05801268 A EP05801268 A EP 05801268A EP 05801268 A EP05801268 A EP 05801268A EP 1807761 A1 EP1807761 A1 EP 1807761A1
Authority
EP
European Patent Office
Prior art keywords
data
unit
mode
arithmetic units
processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP05801268A
Other languages
German (de)
English (en)
Inventor
Thomas Kottke
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from DE200410051992 external-priority patent/DE102004051992A1/de
Priority claimed from DE102004051950A external-priority patent/DE102004051950A1/de
Priority claimed from DE200410051937 external-priority patent/DE102004051937A1/de
Priority claimed from DE200410051964 external-priority patent/DE102004051964A1/de
Priority claimed from DE102004051952A external-priority patent/DE102004051952A1/de
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP1807761A1 publication Critical patent/EP1807761A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1629—Error detection by comparing the output of redundant processing systems
    • G06F11/1641—Error detection by comparing the output of redundant processing systems where the comparison is not performed by the redundant processing components
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/16—Error detection or correction of the data by redundancy in hardware
    • G06F11/1695—Error detection or correction of the data by redundancy in hardware which are operating with time diversity
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30181—Instruction operation extension or modification
    • G06F9/30189—Instruction operation extension or modification according to execution mode, e.g. mode flag
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3885—Concurrent instruction execution, e.g. pipeline or look ahead using a plurality of independent parallel functional units
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/845—Systems in which the redundancy can be transformed in increased performance

Definitions

  • Computer systems for safety-critical applications in particular in the vehicle such as for anti-lock braking systems, the electronic stability program (ESP), X-by-wire systems such as drive-by-wire or steer-by-wire and break-by-wire, etc. or in other networked systems.
  • ESP electronic stability program
  • X-by-wire systems such as drive-by-wire or steer-by-wire and break-by-wire, etc. or in other networked systems.
  • powerful error detection mechanisms and error handling mechanisms are required, in particular to counteract transient errors that arise, for example, in miniaturization of the semiconductor structures of the computer systems. It is relatively difficult to protect the core itself, so the processor.
  • One solution to this is, as mentioned, the use of a dual-computer system or dual core system for fault detection.
  • processors will be discussed below, which also includes cores or computing units conceptually. Description of the embodiments and advantages of the invention
  • the erf ⁇ ndungswashe unit or the inventive method allows the implementation of the two modes in a two-processor system.
  • the two processors operate in error detection mode (F mode)
  • the two processors receive the same data / instructions and operate in performance mode (P mode), so each processor can access the memory. Then, this unit manages the accesses to the just-existing memory or
  • the switching is triggered and / or displayed by a control signal, in particular a mode signal, which is related to the operating mode of at least one arithmetic unit, wherein the control signal is generated in particular externally relative to the arithmetic units.
  • the data to be distributed are forwarded to at least one further component, in particular a computing unit, wherein the data to be distributed are extended before forwarding by an error detection code.
  • the input data can be forwarded to at least one further component, in particular an arithmetic unit, wherein the input data is extended before forwarding by an error detection code.
  • the output data may be forwarded to at least one other component, with the output data being extended by an error detection code before being forwarded.
  • an error signal is advantageously output upon detection of an error due to the error detection code.
  • an error signal is output only in the secure mode (F-mode).
  • a delay component may be contained which, depending on a clock offset of the two arithmetic units in the respective operating mode, delays the leading data by precisely this clock offset.
  • a system is provided with such a device according to the invention, further provided with an external monitoring unit to the unit, which detects errors if an intended switching of the operating modes does not occur. If the two-processor system is operated with a clock offset in F mode and not in P mode, the DVE unit delays the data for the slave accordingly or stores the output data of the master until it is compared with the output data of the slave for error detection can be.
  • FIG. 1 shows a dual-computer system with a first computer 100, in particular one
  • Data terminal DOl Data Out 1
  • DO2 Data Out 2
  • the data bus line 116C which is connected to computer 100 or computer 101 via a data connection Dil (Data In 1) and a data connection DI2 (Data In 2), respectively is.
  • a component 104 is interposed, for example a data memory, in particular a secure data memory o. ⁇ . This component 104 is also supplied with the clock CLK in this example.
  • the components 103 and 104 are representative of any components which are connected via a data bus and / or command bus to the computers of the dual-computer system and corresponding to the accesses via data and / or commands of the dual-processor system with respect to write operations and / or read operations erroneous data and / or commands receive or give away.
  • error prevention are indeed
  • Error detection generators 105, 106 and 107 are provided which generate an error detection such as a parity bit or other error code such as an error correction code, so ECC, o. ⁇ .. are also provided the corresponding Starbuckskennungsprüf healthyen or check Means 108 and 109 for checking the respective misrecognition, for example, the
  • Parity bit or other error code such as ECC.
  • Clock offset a computer here in particular computer 100 erroneous data and / or commands in components, in particular external components such. B. here in particular the memory 103 or 104, but also with respect to other participants or actuators or sensors write or read. Thus, it may also erroneously perform a write access instead of a designated read access by this clock offset.
  • these scenarios lead to errors in the entire system, in particular without clear display possibility which data and / or commands have just been changed incorrectly, which also causes the recovery problem.
  • a delay unit 102 is now connected as shown in the lines of the data bus and / or in the command bus. For reasons of clarity, only the activation in the data bus is shown.
  • Delay the write and read operations delay only the write operations, or, although not preferred, delay the read operations. It can be converted by a change signal, in particular the error signal, a delayed write operation in a read operation to prevent erroneous writing.
  • IllOpDetect Switching between the two modes is detected by the "Switch-Detect" units located between the cache and the processor on the instruction bus and looking to load the IUOp command into the processor.
  • the Switch-Detect unit is unique to each processor, and the Switch-Detect unit does not need to be fault-tolerant because it is duplicated and redundant. On the other hand, it is conceivable to perform this unit fault-tolerant and thus singular, but preferred is the redundant design.
  • ModeSwitch Switching between the two modes is triggered by the "Switch-Detect" unit.If switching from Lock to Split mode, both "Switch-Detect” units will detect switching as both processors are the same Execute program code in Lock mode. The "" switch Detect '"unit of processor 1 detects this 1.5 clocks before the" Switch-Detect "unit of processor 2.
  • The""Modeswitch'" unit halts processor 2 by 2 clocks with the help of the wait signal 2 is also stopped 1.5 clocks later, but only half a clock to synchronize to the system clock, then the status signal is split for the other components, and the two processors continue to work To run tasks, they must diverge in program code, which is done by having read access to the processor ID immediately after switching to split mode This read processor ID is different for each of the two processors, and now becomes a target processor ID, you can then use a Conditional Jump command to move the corresponding processor to a different program location, or switch from split mode to Lo ck mode, this will notice a processor, or one of the two first. This processor will execute program code containing the switchover command. This is now registered by the "Switch-Detect" unit and shares the mode switch
  • both "Switch-Detect" units must notify the Modeswitch unit that they want to switch to split mode, and if the changeover request is only from one unit, the error is detected by the comparison units These continue to receive data from one of the two processors and they do not match the stopped processors.
  • the two processors are in split mode and one does not switch back to lock mode, this can be detected by an external watchdog.
  • the watchdog Upon a trigger signal for each processor, the watchdog notices that the waiting processor is no longer reporting. If there is only one watchdog signal for the processor system, then the triggering of the watchdog must only take place in lock mode. Thus, the Watchdog detect that the mode switch was not made.
  • the mode signal is available as a dual-rail signal. Where "UO" is the lock mode and " ⁇ 01" is the split mode. Errors have occurred with "W and" ⁇ 11 "'.
  • the reloading of the two caches of the processors are controlled by 2 state machines.
  • processor 1 has the higher priority. After a access to the main memory by processor 1 gets now - if both processors want to access the main memory again ⁇ processor2 assigned the memory access permission. These two state machines are implemented for each processor. In lock mode, the output signals of the machines are compared to detect any errors.
  • the data for updating the cache 2 in lock mode are delayed by 1.5 cycles in the IRAM control unit.
  • Control a flag table built. This indicates whether a cache line was written in lock or split mode. In lock mode, the cache line entry value is set to 0 on a cache line reload, and in split mode, even if the cache line is cached from a single cache, to 1. If the processor now executes a memory access in lock mode, then checks if this cache line has been updated in lock mode, ie is the same in both caches. in the
  • Processor 1 coordinates the memory accesses.
  • the DVE consists of the detection of the switching request (IllOPDetect) of the ModeSwitch unit and the Iram and DramControl.
  • the core of the invention is the general mode of operation of the data distribution unit DVE (different data allocation depending on the mode and thus also selection of the operating mode).
  • the illustrated special implementation of the DVE solves the task mentioned at the beginning.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Hardware Redundancy (AREA)
  • Multi Processors (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Debugging And Monitoring (AREA)

Abstract

L'invention concerne une unité et un procédé pour répartir des données d'une source de données dans un système comprenant au moins deux unités de calcul, des moyens de commutation étant utilisés, à travers lesquels au moins deux modes de fonctionnement du système peuvent être commutés. La répartition des données et/ou le choix d'une source de données dépend du mode de fonctionnement.
EP05801268A 2004-10-25 2005-10-25 Procede et dispositif pour repartir des donnees d'au moins une source de donnees dans un systeme a plusieurs processeurs Ceased EP1807761A1 (fr)

Applications Claiming Priority (6)

Application Number Priority Date Filing Date Title
DE200410051992 DE102004051992A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Verzögerung von Zugriffen auf Daten und/oder Befehle eines Mehrprozessorsystems
DE102004051950A DE102004051950A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Taktumschaltung bei einem Mehrprozessorsystem
DE200410051937 DE102004051937A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Synchronisierung in einem Mehrprozessorsystem
DE200410051964 DE102004051964A1 (de) 2004-10-25 2004-10-25 Verfahren und Vorrichtung zur Überwachung einer Speichereinheit in einem Mehrprozessorsystem
DE102004051952A DE102004051952A1 (de) 2004-10-25 2004-10-25 Verfahren zur Datenverteilung und Datenverteilungseinheit in einem Mehrprozessorsystem
PCT/EP2005/055532 WO2006045798A1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour repartir des donnees d'au moins une source de donnees dans un systeme a plusieurs processeurs

Publications (1)

Publication Number Publication Date
EP1807761A1 true EP1807761A1 (fr) 2007-07-18

Family

ID=35677569

Family Applications (5)

Application Number Title Priority Date Filing Date
EP05797084A Expired - Lifetime EP1810145B1 (fr) 2004-10-25 2005-10-25 Procede et dispositif de synchronisation dans un systeme multiprocesseur
EP05801268A Ceased EP1807761A1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour repartir des donnees d'au moins une source de donnees dans un systeme a plusieurs processeurs
EP05811008A Ceased EP1812861A1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour retarder des acces a des donnees et/ou des instructions d'un systeme multiprocesseur
EP05811107A Withdrawn EP1820102A2 (fr) 2004-10-25 2005-10-25 Procede et dispositif de commutation de frequence d'horloge dans un systeme multiprocesseur
EP05801543A Expired - Lifetime EP1807763B1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour surveiller une unite de memoire dans un systeme multiprocesseur

Family Applications Before (1)

Application Number Title Priority Date Filing Date
EP05797084A Expired - Lifetime EP1810145B1 (fr) 2004-10-25 2005-10-25 Procede et dispositif de synchronisation dans un systeme multiprocesseur

Family Applications After (3)

Application Number Title Priority Date Filing Date
EP05811008A Ceased EP1812861A1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour retarder des acces a des donnees et/ou des instructions d'un systeme multiprocesseur
EP05811107A Withdrawn EP1820102A2 (fr) 2004-10-25 2005-10-25 Procede et dispositif de commutation de frequence d'horloge dans un systeme multiprocesseur
EP05801543A Expired - Lifetime EP1807763B1 (fr) 2004-10-25 2005-10-25 Procede et dispositif pour surveiller une unite de memoire dans un systeme multiprocesseur

Country Status (8)

Country Link
US (4) US7853819B2 (fr)
EP (5) EP1810145B1 (fr)
JP (5) JP2008518308A (fr)
KR (4) KR20070083772A (fr)
AT (2) ATE409327T1 (fr)
DE (2) DE502005005284D1 (fr)
RU (1) RU2007119316A (fr)
WO (5) WO2006045801A2 (fr)

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Also Published As

Publication number Publication date
DE502005005490D1 (de) 2008-11-06
KR20070083772A (ko) 2007-08-24
JP2008518309A (ja) 2008-05-29
EP1810145B1 (fr) 2008-09-03
EP1810145A1 (fr) 2007-07-25
EP1820102A2 (fr) 2007-08-22
JP2008518310A (ja) 2008-05-29
EP1807763B1 (fr) 2008-09-24
JP4532561B2 (ja) 2010-08-25
ATE409327T1 (de) 2008-10-15
KR20070067168A (ko) 2007-06-27
WO2006045801A3 (fr) 2006-07-06
KR20070062579A (ko) 2007-06-15
US20080126718A1 (en) 2008-05-29
KR20070083771A (ko) 2007-08-24
EP1812861A1 (fr) 2007-08-01
RU2007119316A (ru) 2008-12-10
ATE407398T1 (de) 2008-09-15
EP1807763A2 (fr) 2007-07-18
WO2006045802A3 (fr) 2007-01-04
JP2008518311A (ja) 2008-05-29
US20090164826A1 (en) 2009-06-25
US7853819B2 (en) 2010-12-14
WO2006045802A2 (fr) 2006-05-04
WO2006045798A1 (fr) 2006-05-04
DE502005005284D1 (de) 2008-10-16
US20080209251A1 (en) 2008-08-28
WO2006045800A1 (fr) 2006-05-04
WO2006045801A2 (fr) 2006-05-04
WO2006045804A1 (fr) 2006-05-04
US20080163035A1 (en) 2008-07-03
JP2008518312A (ja) 2008-05-29
JP2008518308A (ja) 2008-05-29

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