Classifications

• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
  • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/01—Manufacture or treatment
  • H10W72/013—Manufacture or treatment of die-attach connectors
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W90/00—Package configurations
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/071—Connecting or disconnecting
  • H10W72/073—Connecting or disconnecting of die-attach connectors
  • H10W72/07331—Connecting techniques
  • H10W72/07337—Connecting techniques using a polymer adhesive, e.g. an adhesive based on silicone or epoxy
• • H—ELECTRICITY
  • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
  • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
  • H10W72/00—Interconnections or connectors in packages
  • H10W72/30—Die-attach connectors
  • H10W72/351—Materials of die-attach connectors
  • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
  • H10W72/354—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics comprising polymers

Definitions

• the invention relates to a method for assembling two substrates by molecular bonding, at least one of which is made of a semiconductor material.
• a tendency towards complexity in the development of integrated circuits There is nowadays a tendency towards complexity in the development of integrated circuits.
• integrated circuits are no longer simply electronic circuits but integrate other circuits with various functionalities: circuits with optical functions, high frequency circuits and even molecular and bioelectronic circuits.
• silicon is the most commonly used material, but when other functions such as those listed above are used, other materials are clearly more efficient than silicon to perform these additional functions. It therefore appears necessary to be able to integrate other materials on silicon to satisfy the growing development of integrated circuits that are no longer simple electronic circuits.
• the Applicant therefore plans to ensure the integration of one or more materials on a semiconductor material such as silicon by molecular bonding, thus avoiding the use of an adhesive material.
• a semiconductor material such as silicon
• Such adhesion by molecular adhesion ensures a very good mechanical strength, good thermal conductivity and in particular a thickness uniformity of the bonding interface.
• thermal oxide coating is formed on the two different types of substrate.
• CVD Chemical Vapor Deposition
• anglosaxon terminology of an oxide over a thickness of 1 ⁇ m.
• the surfaces thus coated with oxide have a high roughness which is unfavorable for the subsequent molecular adhesion.
• This technique is however not suited to the assembly of thin substrates, for example less than or of the order of 200 ⁇ m in thickness which are likely to be weakened or even broken during the polishing step. and therefore poorly support thinning.
• the chemical mechanical polishing step is difficult to implement on surfaces having a relief or structured.
• InP material that is not directly compatible with the treatment SC (ammonia solution and hydrogen peroxide) conventionally used for saturation in hydroxyl groups.
• the present invention aims to remedy at least one of the aforementioned drawbacks by proposing a method for assembling by molecular bonding two substrates, at least one of which is made of a semiconductor material, characterized in that one of the substrates, called the first substrate has a surface A at least a portion of which is planar and has an initial surface roughness compatible with the molecular bonding, the method comprising the following steps:
• a thin oxide or nitride bonding layer having a thickness of between 10 and 20 nm to allow molecular bonding without prior step polishing
• a thin layer of bonding with a controlled thickness that is sufficiently low is deposited on a surface of a substrate of initial roughness adapted to molecular bonding, so as not to modify the initial surface roughness.
• the surface roughness of the deposited thin film remains sufficiently low and compatible with the molecular adhesion process so as not to require a polishing step after having deposited this thin layer.
• thin substrates therefore fragile, can be assembled thanks to the invention without risk that a polishing step does not damage them, because it is quite possible to deposit a thin layer on a thinned substrate.
• the deposition of a thin layer of oxide or nitride on a substrate renders the surface of the substrate hydrophilic, which then makes it possible to ensure molecular bonding of the hydrophilic type.
• the invention is also of interest when it is desired to assemble by molecular bonding two substrates, one of which has a buried interface of low mechanical strength, which would be incompatible with a mechano-chemical polishing step.
• This interface may be in particular that with the oxide or the nitride bonding.
• the initial surface roughness (rms) of the surface A is less than 0.5 nm.
• the bonding energy that occurs between the two substrates, after molecular adhesion is substantially constant and high value.
• the oxide is chosen from the following oxides: SiO 2 , AbO 3 , metal oxides.
• the nitride is chosen from the following compounds: Si 3 N 4 , AlN,
• the oxide or nitride deposit renders the surface A of the first substrate hydrophilic.
• the surface B of the second substrate intended to be bonded to the surface A thus prepared can be prepared as the surface A
• the saturation of hydroxyl groups is carried out by chemical treatment, for example, in a solution of hydrogen peroxide and ammonia SC type ("Standard Cleaning" in English terminology).
• the saturation of hydroxyl groups is carried out by a non-chemical treatment, for example by means of ultraviolet radiation and in the presence of ozone.
• plasma treatment could be used as another non-chemical treatment.
• the deposition of a bonding layer according to the invention, associated with a UV / ozone treatment, allows such a bonding.
• the preparation step (in terms of roughness) can thus be dissociated from the bonding step and, in particular, it can supply suitable roughness substrates and assemble them according to the invention later.
• the semiconductor material is chosen from among the following materials: silicon, InP, germanium and galium arsenide,
• GaN, SiC, SiGe It can be massive or be obtained by epitaxy.
• the other substrate may be made of an amorphous material such as a glass, such as BPSG.
• amorphous material such as a glass
• BPSG BPSG
• the invention finds a particularly advantageous application when one of the materials to be assembled is an amorphous material with creep capabilities such as a glass.
• the roughness of a glass layer is generally too high to allow for molecular bonding without prior polishing step.
• the polishing of a glass is a difficult operation to implement and therefore undesirable in this case.
• a glass layer has been obtained by deposition on a substrate, for example silicon, it is possible to perform a creep heat treatment operation after deposition of the glass layer.
• the deposition of a thin layer of oxide or nitride followed by a hydrophilization treatment can be carried out with a view to the molecular bonding of this glass layer with a substrate made of a material semiconductor according to the invention.
• the invention relates to a method for assembling a plurality of substrates by molecular bonding with a substrate forming a support, characterized in that each of the substrates, called the first substrate, which is to be assembled with the support substrate, called second substrate, is assembled by the assembly method as briefly described above.
• each first substrate is an integrated circuit carried on the support substrate.
• the assembly method according to the invention makes it possible to obtain a structure comprising at least two substrates comprising between them at least one thin oxide or nitride layer deposited and assembled by molecular bonding.
• the substrates composing this structure may be particularly thin, for example, with a thickness of 200 ⁇ m.
• the substrates which are assembled by molecular bonding according to the invention can also be of a nature such that they do not withstand the treatment in wet chemistry of their surface.
• the assembly method according to the invention makes it possible to obtain a structure comprising more than two substrates (eg circuits integrated) made of different materials and assembled by molecular bonding on a common support substrate via one or more thin layers of the same or different oxide or nitride deposited on the surfaces to be bonded.
• the second substrate is a support substrate for a plurality of substrates each assembled by molecular bonding, by one of their at least locally flat surfaces and provided with an initial surface roughness compatible with molecular bonding, with a surface area of at least locally plane of the support substrate, the molecular bonding being provided by a thin layer of oxide or nitride bonding of sufficiently low thickness to be compatible with the molecular bonding and which is deposited on at least one of at least locally flat surfaces in touch.
• the first substrate and the other substrate or substrates are assembled with the support substrate by surfaces of dimensions that are smaller than those of the total surface of the support substrate.
• the substrates assembled with the support substrate thus form a plurality of mesas which project relative to the surface of the support substrate.
• the invention it is thus possible to integrate, by molecular bonding, chips (integrated circuits) with various functions made of different materials on the same support substrate using at least one thin bonding layer.
• deposited oxide or nitride deposited oxide or nitride.
• Examples include assemblies such as InP on Si or GaAs on Si and more generally assemblies involving materials IN 1 V.
• the entire process can be carried out at low temperature, which is quite suitable for structures whose materials have very different coefficients of thermal expansion: the oxide deposition (densification included) can be achieved between 120 and 380 ° , bonding at ambient temperature and the heat treatment of bonding reinforcement between 200 and 450 ° C.
• a thermal oxide was grown to a thickness of 400 nm.
• the eight plates thus oxidized were then cleaned in a solution of water and sulfuric acid, and then rinsed with water.
• the oxidized and cleaned surfaces of the eight plates were polished by Chemical Mechanical Polishing (CMP) in order to give the surfaces a low roughness of less than 0.5 nm (microroughness measured by AFM).
• CMP Chemical Mechanical Polishing
• the plates 1 to 4 were then cleaned and chemically activated as follows: - cleaning plates 1 to 4 in water, then exposure to ultraviolet radiation in the presence of ozone in order to saturate the oxidized surfaces of the plates with hydroxyl groups ;
• the plates were then rinsed in water and then dried.
• the thus prepared surfaces of the plates 1 to 4 were then contacted in pairs with the oxidized surfaces of the plates 5 to 8 respectively in order to achieve molecular bonding at room temperature.
• the plate 1 has thus been bonded with the plate 5, the plate 2 with the plate 6, the plate 3 with the plate 7 and the plate 4 with the plate 8.
• the four plate structures thus bonded 1/5, 2/6, 3/7 and 4/8 were exposed to infrared radiation, to verify the quality of the molecular bonding and this infrared imaging test revealed no glue failure visible.
• a deposit of a thin layer of SiO 2 oxide with a thickness of 19 nm was made by the PECVD technique on the plates numbered from 1 to 4.
• the plates 3 and 4 were cleaned in a solution of ammonia and hydrogen peroxide (SC), then rinsed in water and dried.
• SC ammonia and hydrogen peroxide
• the prepared surfaces of the plates 1 and 2 were then respectively contacted with the prepared surfaces of the support plates 5 and 6 for molecular bonding to occur at room temperature, thereby giving rise to the bonded 1/5 and 2-ply bonded structures. / 6.
• the prepared surfaces of the plates 3 and 4 have likewise been brought into contact with the prepared surfaces of the support plates 7 and 8, respectively, so that molecular bonding of the contacted surfaces occurs at room temperature, thus resulting in the assembled plate structures glued 3/7 and 4/8.
• a bonding strengthening heat treatment operation was carried out at a temperature of about 200 ° C., thus leading to an interface of good mechanical strength.
• a thin layer of SiO 2 oxide 19 nm thick was deposited according to the PECVD type deposition technique on two flat plates or substrates of silicon. These plates were then cleaned and chemically activated as follows:
• the thus cleaned and chemically activated plates were then contacted by one of their treated surfaces to ensure molecular bonding at room temperature.
• the thus-bonded plates were then subjected to a thermal treatment operation at a temperature of 200 ° C. to reinforce the molecular bonding.
• the bonding energy of the structure thus obtained was measured under conditions identical to the previous conditions and revealed a value of 850 mJ / m 2 , corresponding to a very good quality bonding.
• FIGS. 1 to 9 illustrate the successive steps of assembling an example of a composite assembled structure according to the invention.
• a support substrate 10 for example made of silicon
• a thermal oxide layer thermal SiO 2
• the support substrate is, for example, made of CMOS process silicon, that is to say having undergone technological steps to achieve all or part of electronic components.
• the CMOS substrates are covered with a final passivation layer deposited thick oxide. This thick oxide layer was then polished by mechanical-chemical polishing in order to obtain a level of roughness compatible with molecular bonding, then saturated with hydroxyl groups in order to promote the subsequent molecular bonding of the substrate 10 coated with this layer.
• CMOS process silicon that is to say having undergone technological steps to achieve all or part of electronic components.
• the CMOS substrates are covered with a final passivation layer deposited thick oxide. This thick oxide layer was then polished by mechanical-chemical polishing in order to obtain a level of roughness compatible with molecular bonding, then saturated with hydroxyl groups in order to promote the subsequent molecular bonding of the substrate 10 coated with this layer.
• CMOS process silicon that is to say having undergone technological steps to achieve all or part of electronic components.
• the CMOS substrates
• the substrate has a satisfactory roughness, also be made in the form of a thin oxide layer, thus not requiring a polishing step, and which would subsequently be saturated with hydroxyl groups.
• FIG. 2 shows a referenced substrate 14 made for example in a semiconductor material chosen from silicon, InP, germanium Galium parsenide, SiGe, SiC, GaN, garnets ...
• the chosen material is, for example, InP.
• the surface A of the substrate 14 is coated with a thin bonding layer 16 of silicon nitride (Si 3 N 4 ), of a thickness for example equal to 15 nm obtained by a PECVD type deposition technique.
• the substrate 14 coated with the thin film 16 is cut to form a plurality of substrates S1 referenced 14a, 14b, 14c, each of which is smaller than those of the support substrate 10.
• Each substrate 14a, 14b, 14c is coated with a thin bonding layer 16a, 16b, 16c and the latter are each saturated with hydroxyl groups in order to render the surfaces hydrophilic for subsequent molecular bonding.
• Substrates 14a and 14b coated with a thin layer are then brought into contact by means of this thin layer with the layer 12 of the support substrate 10, as shown in FIG. 4, so that a hydrophilic-type molecular bonding occurs. between the layers put in contact, thus making it possible to assemble the different substrates by molecular bonding by means of hydrogen bonds.
• the substrates 14a and 14b provided with their respective thin layers 16a and 16b form a plurality of mesas (reported integrated circuits) which protrude from the surface of the support substrate. 10.
• a heat treatment of bonding reinforcement can be implemented once the substrates (chips or integrated circuits) have been bonded.
• the oxide may be deposited locally in the areas on which the bonding is to be carried out.
• another substrate 22 is made, for example, in a semiconductor material such as GaAs or, for example, in an amorphous material and is coated with a thin layer 24, for example silicon oxide.
• the thin oxide layer 24 is deposited, for example, by a PECVD type deposition technique and has a thickness, for example, equal to 15 nm. As explained with reference to FIG. 3, the substrate 22 thus coated is cut into several substrates S2 referenced 22a, 22b, 22c, each each coated with a thin oxide layer 24a, 24b, 24c (FIG. 7).
• the substrates thus obtained are then brought into contact via their respective thin layers saturated with hydroxyl groups with the thin layer 20 of the support substrate of FIG. 5 so that a molecular bonding of the surfaces thus brought into contact takes place at ambient temperature. (Figure 8).
• the substrates newly bonded to the support substrate form a plurality of mesas which protrude from the surface of the support substrate.
• finishing operations are implemented in order to remove the thin oxide layer 18 deposited on the upper surface of the mesas formed by the substrates S1 and etching operations may also be implemented.
• the composite structure thus assembled of FIG. 9 comprises a plurality of substrates forming mesas which project relative to the surface of the support and which are, for example, interposed relative to one another.
• the various molecularly bonded substrates via a thin oxide or nitride layer on the surface of the support substrate may be selectively placed in appropriate areas of the support substrate, without necessarily being intercalated between them. one against another.
• the substrates S1 and S2 are made of different materials with respect to each other and different from that of the support substrate.
• structures comprising one or more substrates made of the same material and forming mesas protruding from the support substrate are also conceivable.
• the support substrate has been represented in planar form, but it will be noted that it may have a relief, holes, micromechanical structures, etc.
• the oxide or nitride thin film deposition according to the invention can be carried out over the entire surface of a planar substrate or only on plane preferential zones of the latter, depending on the applications envisaged.
• FIGS. 3 and 7 show substrates (chips or integrated circuits) separated from a single substrate (respectively the substrate of FIGS. 2 and 6) and which comprises a thin layer before separation.
• the thin layer may alternatively be deposited on the plurality of substrates resulting from the separation operation ("dicing" in English terminology).

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• Element Separation (AREA)
• Pressure Welding/Diffusion-Bonding (AREA)
• Recrystallisation Techniques (AREA)
• Mechanical Treatment Of Semiconductor (AREA)

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• 2005
  • 2005-07-06 FR FR0507206A patent/FR2888402B1/fr not_active Expired - Fee Related
• 2006
  • 2006-07-05 US US11/994,636 patent/US20080311725A1/en not_active Abandoned
  • 2006-07-05 WO PCT/FR2006/001596 patent/WO2007006914A1/fr not_active Ceased
  • 2006-07-05 JP JP2008518928A patent/JP2009500819A/ja not_active Withdrawn
  • 2006-07-05 EP EP06778776A patent/EP1900020A1/de not_active Withdrawn

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