EP3075006A1 - Structure de carte de circuits imprimés - Google Patents

Structure de carte de circuits imprimés

Info

Publication number
EP3075006A1
EP3075006A1 EP14805471.1A EP14805471A EP3075006A1 EP 3075006 A1 EP3075006 A1 EP 3075006A1 EP 14805471 A EP14805471 A EP 14805471A EP 3075006 A1 EP3075006 A1 EP 3075006A1
Authority
EP
European Patent Office
Prior art keywords
layer
circuit board
board structure
printed circuit
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Ceased
Application number
EP14805471.1A
Other languages
German (de)
English (en)
Inventor
Johannes Stahr
Mike Morianz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Publication of EP3075006A1 publication Critical patent/EP3075006A1/fr
Ceased legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC]
    • H05K1/185—Printed circuits structurally associated with non-printed electric components associated with components mounted in printed circuit boards [PCB], e.g. insert-mounted components [IMC] associated with components encapsulated in the insulating substrate of the PCBs; associated with components incorporated in internal layers of multilayer circuit boards
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/0296—Conductive pattern lay-out details not covered by sub groups H05K1/02 - H05K1/0295
    • H05K1/0298—Multilayer circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/189—Printed circuits structurally associated with non-printed electric components characterised by the use of flexible or folded printed circuits
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0055—After-treatment, e.g. cleaning or desmearing of holes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/22—Secondary treatment of printed circuits
    • H05K3/26—Cleaning or polishing of the conductive pattern
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H10W70/614—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together the multiple chips being integrally enclosed
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/0198—Manufacture or treatment batch processes
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/11—Printed elements for providing electric connections to or between printed circuits
    • H05K1/115—Via connections; Lands around holes or via connections
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/09—Shape and layout
    • H05K2201/09209—Shape and layout details of conductors
    • H05K2201/095—Conductive through-holes or vias
    • H05K2201/09509—Blind vias, i.e. vias having one side closed
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10166—Transistor
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/10—Details of components or other objects attached to or integrated in a printed circuit board
    • H05K2201/10007—Types of components
    • H05K2201/10174—Diode
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/03—Metal processing
    • H05K2203/0392—Pretreatment of metal, e.g. before finish plating, etching
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2203/00—Indexing scheme relating to apparatus or processes for manufacturing printed circuits covered by H05K3/00
    • H05K2203/12—Using specific substances
    • H05K2203/125—Inorganic compounds, e.g. silver salt
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0035—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material of blind holes, i.e. having a metal layer at the bottom
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/0011—Working of insulating substrates or insulating layers
    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/093—Connecting or disconnecting other interconnections thereto or therefrom, e.g. connecting bond wires or bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/611—Insulating or insulated package substrates; Interposers; Redistribution layers for connecting multiple chips together
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/65—Shapes or dispositions of interconnections
    • H10W70/652—Cross-sectional shapes
    • H10W70/6528—Cross-sectional shapes of the portions that connect to chips, wafers or package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/9413—Dispositions of bond pads on encapsulations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/941—Dispositions of bond pads
    • H10W72/944—Dispositions of multiple bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/951—Materials of bond pads
    • H10W72/952—Materials of bond pads comprising metals or metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/10—Configurations of laterally-adjacent chips

Definitions

  • the invention relates to a printed circuit board structure consisting of at least one insulating layer, at least one conductor layer and at least one embedded component having an outer barrier layer possessing contact pad, wherein at least two interconnects / layers are connected via vias with at least two terminals.
  • the invention further relates to a method for contacting a component embedded in a printed circuit board structure with a printed conductor section by producing plated-through holes from a conductor layer to terminals of the component.
  • the contact pads of the components have copper connection pads, which are constructed on a barrier layer, in particular of nickel.
  • barrier layers are required to prevent diffusion of copper into adjacent layers, in the present case e.g. in an adhesion layer, which consists for example of titanium, titanium-tungsten or chromium.
  • an adhesion layer which consists for example of titanium, titanium-tungsten or chromium.
  • semiconductors e.g. a power MOSFET
  • a contact made of, for example, aluminum for the drain or gate of a MOSFET.
  • An object of the invention is to provide a printed circuit board structure or a method for their production, wherein the production costs can be reduced, the use of extremely thin components, for example, a thickness of the order of 20 m is possible and the use of copper connections to the components to be embedded can be omitted.
  • This object is achieved with a printed circuit board structure of the aforementioned type, in which, according to the invention, each plated-through hole runs from a conductor track / layer directly to the barrier contact layer of the corresponding terminal of the component.
  • the material of the barrier contact layer is selected from the group consisting of nickel, nickel vanadium, platinum, palladium and cobalt.
  • the material of the barrier contact layer is nickel.
  • Cost-effective and technologically easy to control are versions in which the plated through hole is made of copper.
  • an adhesion layer is arranged below the barrier contact layer, wherein the adhesion layer is advantageously selected from the group consisting of titanium, titanium tungsten and chromium.
  • the invention is particularly advantageous when the component is a power component, which may be an IGBT chip / MOSFET or a power diode.
  • the invention advantageously leads to variants in which the printed circuit board structure is at least partially flexible.
  • the object is also achieved with a method of the type mentioned above, in which according to the invention in the region of the terminals of the component in an outer conductor layer at least one opening is made, which extends to a barrier layer of a terminal, and then at least one via from the conductor / Layer is made directly to the barrier layer of the corresponding terminal of the component.
  • electroless copper plating is performed on at least one side of the printed circuit board structure to form a copper layer on the surface and in the openings.
  • the at least one opening is produced by laser cutting.
  • the at least one opening is chemically cleaned before the vias are produced.
  • the chemical cleaning step can usefully reduce the thickness of the barrier layer.
  • a mask is applied to the at least one side of the printed circuit board structure, followed by a galvanic copper plating to produce at least one conductor layer and the completion of plated-through holes and removal of the mask.
  • FIG. 2 shows in a section as a component, for example, a power MOSFET before embedding in a printed circuit board structure and before contacting
  • Fig. 9 shows a variant of a printed circuit board structure according to the invention with a total of four embedded components
  • FIG. 9a shows a section of FIG. 9 with a modified plated through hole in two components.
  • FIGS. 1 a and 1 b which initially explain the principal difference between a contacting of a contact pad of an embedded component according to the prior art on the one hand and according to the invention on the other hand.
  • a component 1a shows in a detailed view a component 1, for example a chip, which, for contacting on its surface, has a flat contact 2, e.g. made of aluminum.
  • a flat contact 2 e.g. made of aluminum.
  • An existing example of titanium, titanium-tungsten or chromium contact adhesion layer 3 is located and this is connected with the interposition of a barrier layer 4 with a contact pad 5, which is usually made of copper.
  • a passivation layer 6 is applied, which consists mostly of silicon nitride.
  • a through-connection is made 9, which, as also explained in more detail below, is prepared by galvanic means.
  • the connection between the conductor track 7 and the terminal 8 of the component 1 thus takes place via a "two-stage" copper connection, namely the plated-through hole 9 and the copper contact pad 5.
  • Fig. Lb shows, in which the same reference numerals as in Fig. 1 a are used for the same parts, that according to the invention, the feedthrough 9 of the conductor 7 extends directly to the barrier layer 4 of the contact pad of the terminal 8.
  • FIG. 2 shows, as an example of a component 1, a power MOSFET which according to the invention is to be embedded in a printed circuit board structure and is contacted on both sides in planar technology.
  • the silicon substrate 1s whose structure is not shown in detail, has on its underside for the drain terminal 8d a flat drain contact 2d made of aluminum, followed by a drain adhesion layer 3 d made of titanium and a drain barrier layer 4d made of nickel.
  • a flat gate contact 2g made of aluminum, above a gate adhesion layer 3g and finally a gate barrier layer 4g are provided for the gate connection 8g.
  • a passivation layer 6 of silicon nitride is also present on the upper side.
  • top refers primarily to the drawings and serve to simplify the description, but not necessarily with any orientation refer to described parts or their orientation in the manufacturing process.
  • FIGS. 3 to 8 wherein the embedding and contacting of the component according to FIG. 2 is shown here with reference to a section of a printed circuit board component.
  • the component 1 is embedded in a printed circuit board, which in the present case consists of an insulating layer 10 with an upper conductor layer 11 and a lower conductor layer 12.
  • the insulating layer 10 may be a commercial prepreg based on an epoxy resin with glass fiber reinforcement, e.g. FR 4 or in other cases e.g. a polyimide with or without reinforcement, the conductor layers are usually copper foils.
  • a window 13 is formed, which frees the underside of the component or the drain terminal 8d.
  • two openings namely a gate opening 14 and a source opening 15 are provided at the top by etching away of copper of the upper conductor layer or laser cutting of the insulating layer 10, up to the gate barrier layer 4g or to the source barrier layer 4s of the gate terminal 8g or of the source terminal 8s.
  • the openings 14, 15 are cleaned with well-known in the field of printed circuit Lochthesesvon, eg by chemical cleaning using potassium permanganate and the thickness of all the barrier layers 4d, 4g, 4s can be reduced by chemical dissolution of the barrier layers.
  • the reduced thickness of the barrier layers 4d, 4g, 4s in FIG. 5 can be seen.
  • the barrier layers 4d, 4g, 4s have a thickness of at least 100 nm or more before cleaning and are reduced by, for example, 50 nm in the cleaning step, for example by up to 500 nm in the case of thicker barrier layers.
  • FIG. 1 An upper copper layer 16 and a lower copper layer 17 are formed, wherein the upper copper layer 16 covers not only the upper conductor layer 11 but also the walls of the openings 14 and 15 and the gate barrier layer 4g and the source barrier layer 4s, respectively. Similarly, the lower copper layer 17 covers the lower conductor layer 12 and the one drain barrier layer 4d.
  • 9 shows by way of example a further embodiment of a printed circuit board structure 22, which is manufactured according to the method described above and contains a total of four components, namely a first MOSFET 23, eg a "high source FET", a second MOSFET 24, eg a "low Source FET ", a drive chip 25 and a capacitor 26, for example of the" Multilayer Cofired Ceramic "type.
  • FIG. 9 also shows two plated-through holes 27, 28 between the upper and lower conductor layers 19, 20, wherein a plated-through hole 28 establishes a connection between source S of the first MOSFET 23 and drain D of the second MOSFET 24.
  • the vias from the bottom conductor layer 20 to the drains of the MOSFETs are split into three and five vias 9, respectively.
  • all plated-through holes of the conductor layers 19, 20 are provided with component reference numbers "9".
  • the drive chip 25 is arranged to the right of the MOSFET 24, and to the right of this the capacitor 26.
  • the structure of the electrode contacting in the MOSFETs 23 and 24 and the drive chip 25 is the same as shown in Fig. 16 and Fig. 2, it thus consists - from the inside to the outside - of a contact layer, a contact adhesion layer and a barrier layer.
  • the two terminals of the capacitor 26 are each internally provided with a contact adhesion layer 26-3 on which a contact barrier layer 26-4 follows.
  • the adhesion layers 26-3 are preferably made of chromium and the barrier layers 26-4 of nickel.
  • the circuit board structure 22 shown in FIG. 9 may contain further components, not shown here, such as power diodes, resistors and inductors.
  • the thickness of the circuit board structure can be kept very low, it is also easily possible to make them at least partially flexible, in which case, for example, offers as a material for the insulating layer polyimide.

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Printing Elements For Providing Electric Connections Between Printed Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Manufacturing Of Printed Wiring (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)

Abstract

L'invention concerne une structure de carte de circuits imprimés (21, 22) constituée d'au moins une couche isolante (10), d'au moins une couche conductrice (11, 12) et d'au moins un composant (1, 23 - 26) encapsulé pourvu de plots de contact (5) possédant une couche barrière extérieure (4). Avec cette structure, au moins deux couches conductrices/tracés conducteurs (19, 20) sont relié(e))s par l'intermédiaire de trous d'interconnexion (9 ; 9d, 9g, 9s) pourvus d'au moins deux raccords (8 ; 8d, 8g, 8s), et chaque trou d'interconnexion (9 ; 9d, 9g, 9s) s'étend d'un tracé conducteur/d'une couche conductrice (11, 12) directement en direction de la couche barrière de contact (4 ; 4d, 4g, 4s) du raccord (8 ; 8d, 8g, 8s) correspondant du composant (1, 23 - 26).
EP14805471.1A 2013-11-27 2014-10-09 Structure de carte de circuits imprimés Ceased EP3075006A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
AT9072013 2013-11-27
PCT/AT2014/050239 WO2015077808A1 (fr) 2013-11-27 2014-10-09 Structure de carte de circuits imprimés

Publications (1)

Publication Number Publication Date
EP3075006A1 true EP3075006A1 (fr) 2016-10-05

Family

ID=52000592

Family Applications (1)

Application Number Title Priority Date Filing Date
EP14805471.1A Ceased EP3075006A1 (fr) 2013-11-27 2014-10-09 Structure de carte de circuits imprimés

Country Status (4)

Country Link
US (2) US10219384B2 (fr)
EP (1) EP3075006A1 (fr)
CN (1) CN105934823A (fr)
WO (1) WO2015077808A1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP3075006A1 (fr) 2013-11-27 2016-10-05 AT & S Austria Technologie & Systemtechnik Aktiengesellschaft Structure de carte de circuits imprimés
AT515101B1 (de) 2013-12-12 2015-06-15 Austria Tech & System Tech Verfahren zum Einbetten einer Komponente in eine Leiterplatte
US11523520B2 (en) 2014-02-27 2022-12-06 At&S Austria Technologie & Systemtechnik Aktiengesellschaft Method for making contact with a component embedded in a printed circuit board
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US11172576B2 (en) 2021-11-09
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US10219384B2 (en) 2019-02-26
CN105934823A (zh) 2016-09-07

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