EP4128326A2 - Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat - Google Patents

Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat

Info

Publication number
EP4128326A2
EP4128326A2 EP21725421.8A EP21725421A EP4128326A2 EP 4128326 A2 EP4128326 A2 EP 4128326A2 EP 21725421 A EP21725421 A EP 21725421A EP 4128326 A2 EP4128326 A2 EP 4128326A2
Authority
EP
European Patent Office
Prior art keywords
power semiconductor
substrate
sintered
layer
template
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP21725421.8A
Other languages
German (de)
English (en)
Inventor
Claus Florian Wagner
Michael Woiton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Siemens AG
Siemens Corp
Original Assignee
Siemens AG
Siemens Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Siemens AG, Siemens Corp filed Critical Siemens AG
Publication of EP4128326A2 publication Critical patent/EP4128326A2/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/401—Package configurations characterised by multiple insulating or insulated package substrates, interposers or RDLs
    • C—CHEMISTRY; METALLURGY
    • C04—CEMENTS; CONCRETE; ARTIFICIAL STONE; CERAMICS; REFRACTORIES
    • C04B—LIME, MAGNESIA; SLAG; CEMENTS; COMPOSITIONS THEREOF, e.g. MORTARS, CONCRETE OR LIKE BUILDING MATERIALS; ARTIFICIAL STONE; CERAMICS; REFRACTORIES; TREATMENT OF NATURAL STONE
    • C04B35/00—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products
    • C04B35/01—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics
    • C04B35/46—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates
    • C04B35/462—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates
    • C04B35/465—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates
    • C04B35/468—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on oxide ceramics based on titanium oxides or titanates based on titanates based on alkaline earth metal titanates based on barium titanates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/01—Manufacture or treatment
    • H10W70/05—Manufacture or treatment of insulating or insulated package substrates, or of interposers, or of redistribution layers
    • H10W70/098—Applying pastes or inks, e.g. screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01204—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01212—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps at a different location than on the final device, e.g. forming as prepeg
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01223—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01221—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition
    • H10W72/01225—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps using local deposition in solid form, e.g. by using a powder or by stud bumping
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/012—Manufacture or treatment of bump connectors, dummy bumps or thermal bumps
    • H10W72/01265—Thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01304—Manufacture or treatment of die-attach connectors using temporary auxiliary members, e.g. using sacrificial coatings or handle substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01321—Manufacture or treatment of die-attach connectors using local deposition
    • H10W72/01323—Manufacture or treatment of die-attach connectors using local deposition in liquid form, e.g. by dispensing droplets or by screen printing
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01321—Manufacture or treatment of die-attach connectors using local deposition
    • H10W72/01325—Manufacture or treatment of die-attach connectors using local deposition in solid form
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/01—Manufacture or treatment
    • H10W72/013—Manufacture or treatment of die-attach connectors
    • H10W72/01365—Thermally treating
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/072—Connecting or disconnecting of bump connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07331—Connecting techniques
    • H10W72/07332—Compression bonding, e.g. thermocompression bonding
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/073—Connecting or disconnecting of die-attach connectors
    • H10W72/07351—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting
    • H10W72/07354—Connecting or disconnecting of die-attach connectors characterised by changes in properties of the die-attach connectors during connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/222—Multilayered bumps, e.g. a coating on top and side surfaces of a bump core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/221—Structures or relative sizes
    • H10W72/225—Bumps having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/241—Dispositions, e.g. layouts
    • H10W72/247—Dispositions of multiple bumps
    • H10W72/248—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/252—Materials comprising solid metals or solid metalloids, e.g. PbSn, Ag or Cu
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/20—Bump connectors, e.g. solder bumps or copper pillars; Dummy bumps; Thermal bumps
    • H10W72/251—Materials
    • H10W72/253—Materials not comprising solid metals or solid metalloids, e.g. polymers or ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/322—Multilayered die-attach connectors, e.g. a coating on a top surface of a core
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/325—Die-attach connectors having a filler embedded in a matrix
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/321—Structures or relative sizes of die-attach connectors
    • H10W72/327—Multiple die-attach connectors having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/331—Shapes of die-attach connectors
    • H10W72/337—Multiple die-attach connectors having different shapes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/341—Dispositions of die-attach connectors, e.g. layouts
    • H10W72/347—Dispositions of multiple die-attach connectors
    • H10W72/348—Top-view layouts, e.g. mirror arrays
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/352—Materials of die-attach connectors comprising metals or metalloids, e.g. solders
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/30—Die-attach connectors
    • H10W72/351—Materials of die-attach connectors
    • H10W72/353—Materials of die-attach connectors not comprising solid metals or solid metalloids, e.g. ceramics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/853—On the same surface
    • H10W72/856—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/877—Bump connectors and die-attach connectors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/921—Structures or relative sizes of bond pads
    • H10W72/926—Multiple bond pads having different sizes
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL

Definitions

  • the invention relates to a method for making contact with a power semiconductor on a substrate.
  • the invention also relates to a power semiconductor module with a power semiconductor and a substrate.
  • the invention also relates to a power converter with at least one power semiconductor module of this type.
  • semiconductor components for example switching elements
  • a converter is to be understood as meaning, for example, a rectifier, an inverter, a converter or a DC voltage converter.
  • switching elements are, for example, transistors, in particular as insulated gate bipolar transistors (IGBTs), as metal oxide semiconductor field effect transistors (MOSFETs) or as field effect transistors.
  • IGBTs insulated gate bipolar transistors
  • MOSFETs metal oxide semiconductor field effect transistors
  • the semiconductor components are usually contacted by means of specific wire bonding technologies and the power modules are attached to a circuit carrier, for example by means of soldering, spring or press connections.
  • the use of bonding wires limits the maximum permissible current density.
  • bonding wires generate parasitic inductances, which limit a maximum achievable switching speed of the switching elements.
  • the laid-open specification EP 3 105 784 A1 describes a method for mounting an electrical component on a substrate. Joining is simplified by a hood in that a contacting structure is provided in this hood and this is joined simultaneously with an additional material when the hood is placed on different joint levels.
  • the laid-open specification DE 2020 12 004 434 Ul describes a shaped metal body to create a connection of a power semiconductor with potential surfaces on the top to form thick wires or ribbons, characterized by a shaped metal body (6a, 6b) that protrudes above one or more potential surfaces, and from which electrical from the rest Metal molded body is separated at least one segment (6b), which extends from a contacting section on a potential surface of the power semiconductor to a laterally spaced apart fastening section for thick wires.
  • the laid-open specification DE 102014 222 819 A1 describes a method for forming a power semiconductor contact structure in a power semiconductor module, which has a substrate and a molded metal body.
  • the formation of the power semiconductor contact structure is first carried out by applying a layer of sintered material with a locally varying thickness on either the shaped metal body or the substrate, followed by sintering the contacting film with the substrate via the properties of the sintered material layer which promote the connection, the contacting film corresponding to the varying thickness of the layer of sintered material gets its shape pronounced.
  • the laid-open specification US 2018/0374813 A1 describes an arrangement with at least one first element that comprises at least one first electrical contacting field; at least one second element which comprises at least one second electrical contact-making field; electrical and mechanical connection means, the electrical and mechanical connection means comprising at least: at least one first metallic interconnection element on the surface of at least the first electrical contact pad; at least one sintered compound of metallic microparticles or nanoparticles, which is stacked with the first metallic interconnection element; where the melting point of the first metallic interconnection elements is higher than the sintering temperature of the metallic microparticles or nanoparticles.
  • EP 0242 626 A2 describes a process for fastening electronic components on a substrate by pressure sintering.
  • the object is achieved according to the invention by a method for contacting a power semiconductor on a substrate, the power semiconductor having at least two electrically isolated contact areas on a side facing the substrate, the at least two electrically isolated contact areas of the power semiconductor using a structured metallic, connecting layer, which comprises at least two essentially closed sintered layers, are firmly bonded to the substrate, the essentially closed sintered layers being applied via a template
  • a first sintered layer is applied to the substrate and at least partially dried, at least one second sintered layer being applied to the first sintered layer and at least partially dried, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer , in particular by pressing, and then by sintering the at least two sintered layers firmly bonded to the substrate, the first sintered layer being applied using a first template, the second sintered layer being applied using a second template and the second template is thicker than the first stencil.
  • the object is achieved according to the invention by a method for producing a power semiconductor module with a power semiconductor and a substrate, the power semiconductor having at least two electrically isolated contact areas on a side facing the substrate, the at least two electrically isolated contact areas of the power semiconductor by means of a structured metallic connecting layer, which comprises at least two essentially closed sintered layers, are materially connected to the substrate, wherein the essentially closed sintered layers are applied via a template, wherein a first sintered layer is applied to the substrate and at least partially dried, wherein at least one second sintered layer is applied to a transfer unit and at least partially dried, wherein the at least partially dried second sintered layer of de
  • the transfer unit is transferred to the first sintered layer, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer being contacted, in particular by pressing, and then being firmly connected to the substrate by sintering the at least two sintered layers.
  • the object is achieved according to the invention by a method for producing a power semiconductor module with a power semiconductor and a substrate, the power semiconductor having at least two electrically isolated contact areas on a side facing the substrate, the at least two electrically isolated contact areas of the power semiconductor by means of a structured metallic connecting layer, which comprises at least two substantially closed sintered layers, are connected to the substrate (4) in a materially bonded manner, the substantially closed sintered layers being applied via a template, a first sintered layer being applied to the substrate and at least one is at least partially dried, at least one second sintered layer being applied to a shaped metal body and at least partially dried, the shaped metal body with one of the at least partially g
  • the dried second sintered layer facing away from the first sintered layer is placed, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer being contacted, in particular by pressing, and then being firmly connected to the substrate by sintering the at least two sintered layers.
  • the object is achieved according to the invention by a method for producing a power semiconductor module with a power semiconductor and a substrate, the power semiconductor having at least two electrically isolated contact areas on a side facing the substrate, the at least two electrically isolated contact areas of the power semiconductor by means of a structured metallic connecting layer, which comprises at least two essentially closed sintered layers, are firmly bonded to the substrate, wherein the essentially closed sintered layers are applied via a template, wherein a first sintered layer is applied to the substrate and at least is partially dried, a metal molded body coated with a second sintered layer being provided, the metal molded body being placed on the first sintered layer with a side facing away from the second sintered layer, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer, in particular by pressing, contacted and then by sintering the at least two sintered layers cohesively connected to the substrate.
  • a structured metallic connecting layer which comprises at least two essentially closed sintered layers
  • a power semiconductor module with a power semiconductor and a substrate, the power semiconductor having at least two electrically isolated contact areas on the side facing the substrate, the at least two electrically isolated contact areas of the power semiconductor by means of a structured metallic Connection layer, which comprises at least two essentially closed sintered layers, are firmly bonded to the substrate, the essentially closed sintered layers being carried over a template, with at least one second sintered layer being applied to a molded metal body, the molded metal body is placed with a side facing away from the second sintered layer on the first sintered layer, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer Contacted r km, in particular by pressing, and then by sintering the at least two sintered layers firmly connected to the substrate.
  • a structured metallic Connection layer which comprises at least two essentially closed sintered layers
  • the object is achieved according to the invention by a power converter with at least one power semiconductor module.
  • the invention is based on the idea of applying a power semiconductor, which has at least two electrically isolated contact areas on a side facing a substrate, to a substrate by sintering in order to achieve improved switching behavior and a higher maximum current density.
  • Examples of such power semiconductors are triacs, transistors or thyristors.
  • the transistors are designed, for example, as insulated gate bipolar transistors (IGBTs), as metal oxide semiconductor field effect transistors (MOSFETs) or as field effect transistors.
  • a substrate is to be understood as a dielectric material which, at least on a side facing the power semiconductor, has an at least partially structured metallization for contacting the power semiconductor.
  • the substrate is designed as a DCB ceramic substrate, which in particular contains special aluminum oxide and / or aluminum nitride and has a copper metallization.
  • the power semiconductor is applied in a flip-chip arrangement on the substrate.
  • the at least two electrically isolated contact areas of the power semiconductor are materially connected to the substrate by means of a structured, in particular metallic, connection layer, the connection layer comprising at least two essentially closed sintered layers.
  • An essentially closed sintered layer is understood to mean a layer which, in contrast to screen printing, is applied with a stencil without a supporting screen, so that there are no functionally identifiable cavities in the connecting layer.
  • An essentially closed sintered layer achieves a high conductivity and a high current-carrying capacity of the connecting layer.
  • the power semiconductor is contacted by the connecting layer at least 70 gm, in particular at least 200 gm, spaced from the substrate. Such a distance ensures that electromagnetic fields occurring on the power semiconductor, which occur for example in the area of a guard ring, do not noticeably interact with the substrate, so that the switching behavior of the power semiconductor and insulation in the edge area are too close to the Substrate is not noticeably influenced, which leads to an increase in service life.
  • the at least two essentially closed sintered layers are produced from a suspension which, in particular, contains metallic, solid particles and a binding agent.
  • a suspension which, in particular, contains metallic, solid particles and a binding agent.
  • silver sinter paste is used.
  • Such a suspension achieves a high conductivity and a high current-carrying capacity of the connecting layer.
  • a first sintered layer is applied to the substrate and at least partially dried, at least one second sintered layer being applied to the first sintered layer and at least partially dried, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer, in particular by pressing, and then by sintering the at least two sintered layers firmly connected to the substrate.
  • drying which takes place, for example, at a temperature between 100 ° C. and 150 ° C., in particular between 115 ° C. and 125 ° C.
  • a binder for example, is at least partially removed.
  • the sintering temperature is, for example when using Silver sintering paste, between 220 ° C and 260 ° C, especially between 235 ° C and 245 ° C.
  • an improved structuring in particular in a direction orthogonal to the substrate surface, is sufficient.
  • an improved wall steepness of the connecting layer is achieved when printing several thin layers.
  • Such a multi-layer printing process therefore prevents the at least two electrically isolated contact areas from influencing each other electrically and / or magnetically or even being short-circuited, even with a layer thickness of, for example, at least 70 ⁇ m.
  • the first sintered layer is applied by means of a first template, the second sintered layer being applied by means of a second template and the second template being thicker than the first template.
  • the second template is essentially twice as thick as the first template.
  • the templates are designed in such a way that they rest on the substrate, in particular flat, during the application of the respective sintered layer. The use of such templates prevents the first sintered layer from deforming when the second sintered layer is applied.
  • a first sintered layer is applied to the substrate and at least partially dried, at least one second sintered layer being applied to a transfer unit and at least partially dried, the at least partially dried second sintered layer from the transfer unit the first sintered layer is transferred, the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer, in particular by pressing, contacted and then by sintering the at least two sintered layers are firmly bonded to the substrate.
  • the first sintered layer is applied to the substrate by means of a first template, the second sintered layer being applied with the first template, which is arranged in an inverted manner.
  • the transfer unit is designed, for example, as a Teflon-coated sheet metal, in particular sheet aluminum, in order to enable a multiple transfer of the at least one second sintered layer.
  • the transfer takes place by means of pressure and an, in particular slight, increase in temperature, where the temperature for transferring the at least one second sintered layer is significantly below the sintering temperature.
  • the first sintered layer is applied to the substrate by means of a first template, the second sintered layer being applied to the transfer unit by means of a template which is mirror-symmetrical to the first template.
  • the application by means of the mirror-symmetrical template takes place in particular in parallel in time, which saves time.
  • any number of sintered layers can be produced on transfer units.
  • a first sintered layer is applied to the substrate and at least partially dried, at least one second sintered layer being applied to a metal molding and at least partially dried, the metal molding with one of the at least partially dried second sinters
  • the side facing away from the layer is placed on the first sintered layer, the at least two electrically insulated contact areas of the power semiconductor on the second sintered layer, in particular by pressing, contacted and then firmly connected to the substrate by sintering the at least two sintered layers.
  • the shaped metal body is made, for example, of an electrically and thermally conductive material such as copper, silver, gold, aluminum, cobalt, platinum, molybdenum and / or their alloys.
  • the metal molding achieves an improved wall steepness of the connecting layer and simplifies sintering, in particular for thick layers, for example of at least 70 ⁇ m.
  • the metal molded body comprises at least two metal plates, the at least one second sintered layer being applied to the at least two metal plates of the metal molded body by means of at least one first template.
  • the metal plates are made, for example, from an electrically and thermally conductive material such as copper, silver, gold, aluminum, cobalt, platinum and / or their alloys.
  • the metal platelets achieve an improved wall steepness of the connec tion layer and simplify the sintering, especially for thick layers, for example of at least 70 ⁇ m.
  • a further embodiment provides that a first sintered layer is applied to the substrate and at least partially dried, a metal molded body with a second sintered layer being provided, the metal molded body being placed on the first sintered layer with a side facing away from the second sintered layer, wherein the at least two electrically isolated contact areas of the power semiconductor on the second sintered layer are contacted, in particular by pressing, and thereupon are firmly connected to the substrate by sintering the at least two sintered layers.
  • the provision of a shaped metal body with a sintered layer saves time.
  • FIG. 1 shows a schematic representation of a first embodiment of a method for contacting a power semiconductor on a substrate
  • FIG. 2 shows a schematic sectional illustration of a first embodiment of a template
  • FIG. 3 shows a schematic sectional illustration of a second embodiment of a template
  • FIG. 4 shows a schematic representation of a second embodiment of a method for contacting a power semiconductor on a substrate
  • FIG. 5 shows a schematic representation of a third embodiment of a method for contacting a power semiconductor on a substrate
  • FIG. 6 shows a schematic representation of a fourth embodiment of a method for contacting a power semiconductor on a substrate
  • FIG. 7 shows a schematic illustration of a power semiconductor module.
  • the described components of the embodiments each represent individual features of the invention that are to be considered independently of one another, which also further develop the invention independently of one another and are therefore to be regarded as part of the invention individually or in a combination other than the one shown . Furthermore, the described embodiments can also be supplemented by further features of the invention already described.
  • the substrate is designed as a DCB ceramic substrate, which contains, for example, aluminum oxide and / or aluminum nitride and an at least partially structured metallization 6, in particular Kup fermetallmaschine having.
  • the power semiconductor 2 is exemplified as an IGBT (Insulated Gate Bipolar Transistor) and is applied to the substrate 4 in a flip-chip arrangement.
  • the IGBT has two electrically mutually insulated contact areas 10, 12, the first contact area 10 being designed as an emitter contact E and the second contact area 12 being designed as a gate contact G.
  • the contact areas are designed in particular as pads and have a metallization.
  • a third contact area 14, which is designed as a collector contact C, is located on a side 16 facing away from the substrate 4.
  • the power semiconductor 2 has an electrically insulating intermediate area 2a between the contact areas 10, 12.
  • the power semiconductor 2 has a guard ring 2b, which comprises, for example, a glass or polyamide cover with a thickness of 10-15 ⁇ m.
  • the power semiconductor 2 can for example also be designed as a field effect transistor or bipolar transistor.
  • a closed first sintered layer 20 is applied to the substrate 4 by means of a first template 18 and at least partially dried after removing the first template 18.
  • the first template 18 has, for example, a first thickness dl of 80-100 ⁇ m and is located during the application of the first sintered layer 20, in particular more planar, on the substrate 4.
  • the first sintered layer 20 is made, for example, from a suspension which contains metallic solid particles and an, in particular organic, binder.
  • silver sintering paste is used for the first sintered layer.
  • the binder is at least partially removed by drying at a temperature between 100 ° C. and 150 ° C., in particular between 115 ° C. and 125 ° C.
  • a closed second sintered layer 24 is applied to the first sintered layer 20 by means of a second template 22 and, after the removal of the second template 22, is at least partially dried.
  • the second sintered layer 24 is made of the same material as the first sintered layer 20 and is dried analogously to the first sintered layer 20.
  • the second template 22 has, for example, a second thickness d2 of 120-200 ⁇ m.
  • the second template 22 rests on the substrate 4, in particular over a large area, during the application of the second sintered layer 24.
  • the two contact areas 10, 12 of the power semiconductor 2, which are electrically isolated from one another, are contacted on the second sintered layer 24, in particular by being pressed on.
  • the power semiconductor 2 is then firmly connected to the substrate 4 by sintering the sintered layers 20, 24.
  • the sintering temperature for example when using silver sintering paste, is between 220 ° C and 260 ° C, in particular between 235 ° C and 245 ° C. Both during drying and during sintering, the dimensions of the sintered layers 20, 24 are reduced depending on the material used. This effect is not shown in the schematic representation in FIG.
  • the sintering produces a connecting layer 26 through which the power semiconductor 2 is contacted at a distance D of at least 70 ⁇ m, in particular at least 200 ⁇ m, from the substrate 4.
  • 2 shows a schematic sectional illustration of a first embodiment of a first template 18.
  • the first template 18 comprises a first recess 28, for example for an emitter contact E, and a second recess 30, for example for a gate contact G.
  • the second recess 30 is arranged in a corner region of the first recess 28, where the first template 18 comprises two orthogonally arranged connecting webs 32 which connect the second recess 30 to the first recess.
  • the first template 18 is designed in one piece for both recesses 28, 30.
  • the further embodiment of the first template 18 in FIG. 2 corresponds to that in FIG. 1.
  • FIG. 3 shows a schematic sectional illustration of a second embodiment of a first template 18, the second recess 30 being arranged essentially in the center with respect to a longitudinal side of the first recess 28.
  • the first template 18 comprises three orthogonally arranged connecting webs 32 which connect the second recess 30 to the first recess 28.
  • the further embodiment of the first template 18 in FIG. 3 corresponds to that in FIG.
  • FIG. 4 shows a schematic representation of a second embodiment of a method for contacting a power semiconductor 2 on a substrate 4.
  • a closed third sintered layer 36 is applied to the second sintered layer 24 by means of a third template 34 and after removing the third template 34 at least partially dried.
  • the third sintered layer 36 is made of the same material as the first sintered layer 20 and the second sintered layer 24. Like the second sintered layer 24, it is dried analogously to the first sintered layer 20.
  • the two electrically insulated contact areas 10, 12 of the power semiconductor 2 on the third sintered layer 36 are contacted, in particular by being pressed on.
  • the power semiconductor 2 is then sintered by sintering the sintered layers 20, 24, 36 Cohesively connected to the substrate 4.
  • the sintering produces a connecting layer 26 through which the power semiconductor 2 is contacted at a distance D of at least 70 ⁇ m, in particular at least 200 ⁇ m, from the substrate 4.
  • the further method for making contact with the power semiconductor 2 in FIG. 4 corresponds to the method in FIG.
  • FIG. 5 shows a schematic representation of a third embodiment of a method for contacting a power semiconductor 2 on a substrate 4.
  • a closed first sintered layer 20 is applied to the substrate 4 and, after the first stencil 18 has been removed, at least partially dried .
  • at least one second sintered layer 24 is applied to a transfer unit 38 and at least partially dried.
  • the second sintered layer 24 is applied by means of a template 40 which is mirror-symmetrical to the first template 18.
  • the second sintered layer 24 is applied with the first template 18 arranged in an inverted manner.
  • the transfer unit 38 is, for example, Teflon-coated in order to allow easy transfer of the second sintered layer 24.
  • the at least partially dried second sintered layer 24 is then transferred from the transfer unit 38 to the first sintered layer 20.
  • the transfer takes place by pressure and an, in particular small, increase in temperature, where the temperature for transferring the second sintered layer 24 is well below the sintering temperature.
  • further sintered layers are transferred analogously to the second sintered layer 24 from a transfer unit 38.
  • the two contact areas 10, 12 of the power semiconductor 2, which are electrically isolated from one another, are contacted on the second sintered layer 24, in particular by being pressed on.
  • the power semiconductor 2 is then made of material by sintering the sintered layers 20, 24 closely connected to the substrate 4.
  • the sintering produces a connecting layer 26 through which the power semiconductor 2 is contacted at a distance D of at least 70 ⁇ m, in particular at least 200 ⁇ m, from the substrate 4.
  • the further method for making contact with the power semiconductor 2 in FIG. 5 corresponds to the method in FIG.
  • FIG. 6 shows a schematic representation of a fourth embodiment of a method for contacting a power semiconductor 2 on a substrate 4.
  • a closed first sintered layer 20 is applied to the substrate 4 using a first template 18 and at least partially dried after the first template 18 has been removed .
  • at least one second sintered layer 24 is applied to a metal molded body 42 and at least partially dried.
  • the metal molded body 42 is divided into two metal plates 42a, 42b, which are electrically insulated from one another and are made from a material such as copper, silver, gold, aluminum, cobalt, platinum and / or their alloys with good electrical and thermal conductivity.
  • the metal plates 42a, 42b of the metal molding 42 each have a thickness of 10 gm to 200 gm, a first metal plate 42a having a contour that is adapted to the first contact area 10 of the power semiconductor 2 and a second metal plate 42b Has contour which is adapted to the second contact area 12 of the power semiconductor 2.
  • the shaped metal body 42 can also comprise just one metal plate 42a, which is connected to the contact area 10, 12 of the power semiconductor 2, which has the larger area.
  • one metal plate 42a is connected to the emitter contact E, while the gate contact G is connected to the substrate 4 by means of dispensing or by means of jetting.
  • a shaped metal body already coated with the second sintered layer 24 is provided by 42.
  • the shaped metal body 42 is then arranged with a side facing away from the at least partially dried second sintered layer on the first sintered layer 20, so that the second sintered layer 24 forms the topmost layer.
  • the molded metal body 42 is contacted by being pressed onto the first sintered layer 20.
  • the two contact areas 10, 12 of the power semiconductor 2, which are electrically isolated from one another, are contacted on the second sintered layer 24, in particular by being pressed on.
  • the power semiconductor 2 is then firmly connected to the substrate 4 by sintering the sintered layers 20, 24.
  • the sintering produces a connecting layer 26 through which the power semiconductor 2 is contacted at a distance D of at least 70 ⁇ m, in particular at least 200 ⁇ m, from the substrate 4.
  • the connecting layer 26 in FIG. 6 comprises the shaped metal body 42.
  • the further method for contacting the power semiconductor 2 in FIG. 6 corresponds to the method in FIG.
  • FIG. 7 shows a schematic representation of a power semiconductor module 44, with the power semiconductor 2 being contacted, for example, as described in FIG.
  • the third contact area 14, designed as collector contact C is firmly connected via a further connecting layer 46 to an, in particular multi-layer, further substrate 48, which has an, in particular multi-layer, structured metallization 6, in particular copper metallization.
  • the further connecting layer 46 has, for example, at least one sintered layer.
  • the power semiconductor module 44 comprises connecting elements 50, 52 for producing a connection between the metalizations 6 of the substrates 4, 48.
  • the first contact area 10 embodied as an emitter contact E is connected to the first connecting element 50
  • the te contact G executed second contact region 12 is connected to the second connecting element 52.

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Materials Engineering (AREA)
  • Structural Engineering (AREA)
  • Organic Chemistry (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Abstract

L'invention concerne un procédé de mise en contact d'un semi-conducteur de puissance (2) sur un substrat (4). L'invention vise à obtenir un meilleur comportement de commutation et une densité de courant maximale augmentée. A cet effet, le semi-conducteur de puissance (2) présente sur une face (8) tournée vers le substrat au moins deux zones de contact (10, 12) isolées électriquement l'une de l'autre, lesdites au moins deux zones de contact (10, 12) isolées électriquement l'une de l'autre du semi-conducteur de puissance (2) étant reliées au substrat (4) par liaison de matière, au moyen d'une couche de liaison (26) structurée, en particulier métallique, qui comprend au moins deux couches frittées (20, 24, 36) sensiblement fermées.
EP21725421.8A 2020-06-23 2021-04-30 Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat Pending EP4128326A2 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
EP20181634 2020-06-23
PCT/EP2021/061372 WO2021259536A2 (fr) 2020-06-23 2021-04-30 Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat

Publications (1)

Publication Number Publication Date
EP4128326A2 true EP4128326A2 (fr) 2023-02-08

Family

ID=71138531

Family Applications (1)

Application Number Title Priority Date Filing Date
EP21725421.8A Pending EP4128326A2 (fr) 2020-06-23 2021-04-30 Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat

Country Status (4)

Country Link
US (1) US20230343745A1 (fr)
EP (1) EP4128326A2 (fr)
CN (1) CN115917719A (fr)
WO (1) WO2021259536A2 (fr)

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
IN168174B (fr) 1986-04-22 1991-02-16 Siemens Ag
JP3420203B2 (ja) * 2000-10-27 2003-06-23 Ｎｅｃエレクトロニクス株式会社 ハンダバンプの形成方法
JP2004228375A (ja) * 2003-01-23 2004-08-12 Seiko Epson Corp バンプの形成方法、デバイス、及び電子機器
JP2006222323A (ja) * 2005-02-14 2006-08-24 Compeq Manufacturing Co Ltd ソルダーバンプの形成方法
JP2011060964A (ja) * 2009-09-09 2011-03-24 Tamura Seisakusho Co Ltd バンプの形成方法
DE102011005322B4 (de) * 2011-03-10 2017-04-06 Semikron Elektronik Gmbh & Co. Kg Verfahren zur Herstellung eines Leistungshalbleitersubstrates
DE202012004434U1 (de) 2011-10-15 2012-08-10 Danfoss Silicon Power Gmbh Metallformkörper zur Schaffung einer Verbindung eines Leistungshalbleiterchips mit oberseitigen Potentialflächen zu Dickdrähten
DE102012207652A1 (de) * 2012-05-08 2013-11-14 Robert Bosch Gmbh Zweistufiges Verfahren zum Fügen eines Halbleiters auf ein Substrat mit Verbindungsmaterial auf Silberbasis
WO2015029152A1 (fr) * 2013-08-28 2015-03-05 株式会社日立製作所 Dispositif à semi-conducteur
DE102014206608A1 (de) 2014-04-04 2015-10-08 Siemens Aktiengesellschaft Verfahren zum Montieren eines elektrischen Bauelements, bei der eine Haube zum Einsatz kommt, und zur Anwendung in diesem Verfahren geeignete Haube
TW201611198A (zh) * 2014-04-11 2016-03-16 阿爾發金屬公司 低壓燒結粉末
SG11201608656PA (en) * 2014-05-05 2016-12-29 Heraeus Deutschland Gmbh & Co Kg Method for applying dried metal sintering compound by means of a transfer substrate onto a carrier for electronic components, corresponding carrier, and the use thereof for sintered connection to elec
KR20190016142A (ko) * 2014-06-12 2019-02-15 알파 어?블리 솔루션 인크. 재료들의 소결 및 그를 이용하는 부착 방법들
DE102014222819B4 (de) 2014-11-07 2019-01-03 Danfoss Silicon Power Gmbh Leistungshalbleiterkontaktstruktur mit Bondbuffer sowie Verfahren zu dessen Herstellung
FR3047111B1 (fr) 2016-01-26 2018-03-23 Commissariat A L'energie Atomique Et Aux Energies Alternatives Assemblage comprenant des moyens d'interconnexion mixtes comportant des elements intermediaires d'interconnexion et des joints frittes metalliques et procede de fabrication
DE102016225654A1 (de) * 2016-12-20 2018-06-21 Robert Bosch Gmbh Leistungsmodul mit einem in Etagen ausgebildeten Gehäuse
US10002821B1 (en) * 2017-09-29 2018-06-19 Infineon Technologies Ag Semiconductor chip package comprising semiconductor chip and leadframe disposed between two substrates
KR102048478B1 (ko) * 2018-03-20 2019-11-25 엘지전자 주식회사 양면냉각형 파워 모듈 및 그의 제조 방법
CN111819684A (zh) * 2018-03-23 2020-10-23 三菱综合材料株式会社 电子组件安装模块
EP3690936A1 (fr) * 2019-01-29 2020-08-05 Heraeus Deutschland GmbH & Co KG Procédé de fabrication d'un système d'espacement avec un logement pour une puce, système d'espacement correspondant et son utilisation pour contacter une puce à un substrat par frittage
WO2021221460A1 (fr) * 2020-04-28 2021-11-04 주식회사 아모센스 Film de transfert adhésif et procédé de fabrication d'un substrat de module de puissance en utilisant celui-ci

Also Published As

Publication number Publication date
CN115917719A (zh) 2023-04-04
WO2021259536A3 (fr) 2022-07-07
US20230343745A1 (en) 2023-10-26
WO2021259536A2 (fr) 2021-12-30

Similar Documents

Publication Publication Date Title
EP4128337B1 (fr) Module de puissance pourvu d'au moins trois unités de puissance
EP3625823B1 (fr) Module de puissance comprenant au moins un semi-conducteur de puissance
DE10102621B4 (de) Leistungsmodul
DE102005047106B4 (de) Leistungshalbleitermodul und Verfahren zur Herstellung
WO2021254679A1 (fr) Module semi-conducteur de puissance comprenant au moins un élément semi-conducteur de puissance
EP3794641A1 (fr) Dispositif d'évacuation de chaleur pour un module de puissance à semi-conducteurs
DE10314172B4 (de) Verfahren zum Betreiben einer Anordnung aus einem elektrischen Bauelement auf einem Substrat und Verfahren zum Herstellen der Anordnung
WO2007033829A2 (fr) Module semi-conducteur de puissance et son procede de production
DE102012215656B4 (de) Verfahren zur Herstellung eines Leistungshalbleitermoduls
WO2019063533A1 (fr) Composant et son procédé de production
WO2018037047A1 (fr) Module de puissance, procédé de fabrication et circuit électronique de puissance
DE102017211336A1 (de) Leistungsmodul mit oberflächenmontierten elektrischen Kontaktierungselementen
WO2021259536A2 (fr) Procédé de mise en contact d'un semi-conducteur de puissance sur un substrat
EP4211719B1 (fr) Module semi-conducteur pourvu d'au moins un élément semi-conducteur
EP3940769A1 (fr) Module semi-conducteur pourvu d'au moins un élément semi-conducteur et d'un substrat
DE112022000346T5 (de) Halbleitervorrichtung und Verfahren zum Herstellen derselben
DE102015115133B3 (de) Verfahren zum Verbinden eines Kühlkörpers mit wenigstens einem Schaltungsträger durch Aufschrumpfen
WO2017093116A1 (fr) Module électronique de puissance
EP4500579B1 (fr) Procédé de fabrication d'un ensemble semi-conducteur doté d'un élément semi-conducteur et d'un substrat et ensemble semi-conductuer correspondant
DE102025107068B3 (de) Leistungshalbleitergehäuse mit einer elektrisch leitfähigen paste und leistungselektroniksystem
EP4552155B1 (fr) Agencement doté d'au moins un composant passif
EP4199075A1 (fr) Module électronique comprenant un caloduc pulsant doté d'une structure de canal
DE102006040838A1 (de) Elektrische Leistungspackung mit zwei Substraten mit mehreren Halbleiterchips und elektronischen Komponenten
EP4235771A1 (fr) Dispositif semi-conducteur pourvu d'au moins un élément semi-conducteur, d'une première couche de matière et d'une seconde couche de matière
EP4604178A1 (fr) Dispositif semi-conducteur de puissance comprenant un support de circuit, un dissipateur thermique et un circuit électronique et procédé de fabrication de ce dispositif

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: UNKNOWN

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20221028

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)