ES2064364T3 - Sistema de control de la prioridad de acceso para memoria principal para un ordenador. - Google Patents

Sistema de control de la prioridad de acceso para memoria principal para un ordenador.

Info

Publication number
ES2064364T3
ES2064364T3 ES88402360T ES88402360T ES2064364T3 ES 2064364 T3 ES2064364 T3 ES 2064364T3 ES 88402360 T ES88402360 T ES 88402360T ES 88402360 T ES88402360 T ES 88402360T ES 2064364 T3 ES2064364 T3 ES 2064364T3
Authority
ES
Spain
Prior art keywords
access
warehouse
unit
responses
exit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES88402360T
Other languages
English (en)
Inventor
Nobuo Uchida
Yuji Oinaga
Mikio Itoh
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from JP23370487A external-priority patent/JPS6478337A/ja
Priority claimed from JP62256794A external-priority patent/JPH0199143A/ja
Priority claimed from JP62314745A external-priority patent/JPH0610801B2/ja
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Application granted granted Critical
Publication of ES2064364T3 publication Critical patent/ES2064364T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/18—Handling requests for interconnection or transfer for access to memory bus based on priority control

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Multi Processors (AREA)

Abstract

UN SISTEMA DE CONTROL DE PRIORIDAD DE ACCESO PARA ALMACEN PRINCIPAL DE COMPUTADOR, PARA CONTROLAR UNA TRANSMISION DE SEÑAL AL ALMACEN PRINCIPAL (70,71), TRAS RECIBIR UNA PLURALIDAD DE PETICIONES DE ACCESO AL ALMACEN PROCEDENTES DE AL MENOS UN PROCESADOR (10-14) RELACIONADO CON EL ALMACEN PRINCIPAL. EL SISTEMA INCLUYE UNA PRIMERA UNIDAD DE PASO DE SOLICITUD DE ACCESO (20-24) PARA TOMAR, AL MENOS TEMPORALMENTE, UNA DIRECCION SEGMENTADA DE LAS PETICIONES DE ACCESO AL ALMACEN PROCEDENTES DEL PROCESADOR; UNA PRIMERA UNIDAD DE CONTROL (3) QUE RESPONDE A LA SALIDA DE LA PRIMERA UNIDAD DE PASO DE SOLICITUDES DE ACCESO PARA COMPROBAR LAS CONDICIONES DE CONFLICTO EN EL BUS Y LAS CONDICIONES DE PROHIBICION PARA UN SEGMENTO DE ALMACEN DE DESTINO DETERMINADO POR LA DIRECCION DE LA SOLICITUD DE ACCESO AL ALMACEN; UNA SEGUNDA UNIDAD DE PASO DE SOLICITUD DE ACCESO (5) QUE RESPONDE A LA SALIDA DE LA PRIMERA UNIDAD DE CONTROL (3) PARA TOMAR AL MENOS TEMPORALMENTE UNA DIRECCION DE INTRA-SEGMENTO DE LA SOLICITUD DE ACCESO AL ALMACEN; Y UNA SEGUNDA UNIDAD DE CONTROL (4) QUE RESPONDE A LA SALIDA DE LA SEGUNDA UNIDAD DE PASO DE SOLICITUD DE ACCESO (5) PARA COMPROBAR LA CONDICION DE OCUPADO DEL ALMACEN LOGICO EN LOS SEGMENTOS DE ALMACENAMIENTO.
ES88402360T 1987-09-19 1988-09-19 Sistema de control de la prioridad de acceso para memoria principal para un ordenador. Expired - Lifetime ES2064364T3 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
JP23370487A JPS6478337A (en) 1987-09-19 1987-09-19 Control system for main memory access priority order
JP62256794A JPH0199143A (ja) 1987-10-12 1987-10-12 主記憶アクセス制御方法
JP62314745A JPH0610801B2 (ja) 1987-12-10 1987-12-10 主記憶アクセス制御装置

Publications (1)

Publication Number Publication Date
ES2064364T3 true ES2064364T3 (es) 1995-02-01

Family

ID=27332027

Family Applications (1)

Application Number Title Priority Date Filing Date
ES88402360T Expired - Lifetime ES2064364T3 (es) 1987-09-19 1988-09-19 Sistema de control de la prioridad de acceso para memoria principal para un ordenador.

Country Status (6)

Country Link
US (1) US5073871A (es)
EP (1) EP0309330B1 (es)
AU (1) AU592717B2 (es)
CA (1) CA1310429C (es)
DE (1) DE3852261T2 (es)
ES (1) ES2064364T3 (es)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH01169565A (ja) * 1987-12-24 1989-07-04 Fujitsu Ltd マルチプロセッサ制御方式
US5214769A (en) * 1987-12-24 1993-05-25 Fujitsu Limited Multiprocessor control system
JPH01303543A (ja) * 1988-05-31 1989-12-07 Fujitsu Ltd メモリアクセス制御装置
FR2644260B1 (fr) * 1989-03-08 1993-10-29 Nec Corp Dispositif de commande d'acces en memoire pouvant proceder a une commande simple
KR930002316B1 (ko) * 1989-05-10 1993-03-29 미쯔비시덴끼 가부시끼가이샤 버스제어방법 및 화상처리 장치
JPH0648477B2 (ja) * 1990-09-17 1994-06-22 日通工株式会社 マルチプロセッサシステムにおけるバス獲得方法
US5515523A (en) * 1991-06-03 1996-05-07 Digital Equipment Corporation Method and apparatus for arbitrating conflicts by monitoring number of access requests per unit of time in multiport memory systems
US5423008A (en) * 1992-08-03 1995-06-06 Silicon Graphics, Inc. Apparatus and method for detecting the activities of a plurality of processors on a shared bus
JP3010947B2 (ja) * 1992-11-26 2000-02-21 日本電気株式会社 メモリアクセス制御装置
US6055607A (en) * 1996-12-23 2000-04-25 Unisys Corporation Interface queue with bypassing capability for main storage unit
DE10110578B4 (de) * 2000-03-29 2004-06-03 International Business Machines Corporation Hierarchisches Prioritätsfilter mit integrierter Serialisierung

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3812473A (en) * 1972-11-24 1974-05-21 Ibm Storage system with conflict-free multiple simultaneous access
US4212057A (en) * 1976-04-22 1980-07-08 General Electric Company Shared memory multi-microprocessor computer system
US4314335A (en) * 1980-02-06 1982-02-02 The Perkin-Elmer Corporation Multilevel priority arbiter
US4395753A (en) * 1980-06-26 1983-07-26 Gte Automatic Electric Labs Inc. Allocation controller providing for access of multiple common resources by a plurality of central processing units
US4445174A (en) * 1981-03-31 1984-04-24 International Business Machines Corporation Multiprocessing system including a shared cache
US4875161A (en) * 1985-07-31 1989-10-17 Unisys Corporation Scientific processor vector file organization
JPH0628051B2 (ja) * 1986-04-25 1994-04-13 株式会社日立製作所 記憶制御方式

Also Published As

Publication number Publication date
EP0309330B1 (en) 1994-11-30
DE3852261D1 (de) 1995-01-12
CA1310429C (en) 1992-11-17
EP0309330A2 (en) 1989-03-29
AU2231888A (en) 1989-05-04
US5073871A (en) 1991-12-17
EP0309330A3 (en) 1991-05-08
DE3852261T2 (de) 1995-04-06
AU592717B2 (en) 1990-01-18

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