ES2084603T3 - Fabricacion de circuitos integrados, incluyendo metodo de baja temperatura para elaborar estructuras de siliciuro. - Google Patents

Fabricacion de circuitos integrados, incluyendo metodo de baja temperatura para elaborar estructuras de siliciuro.

Info

Publication number
ES2084603T3
ES2084603T3 ES89310697T ES89310697T ES2084603T3 ES 2084603 T3 ES2084603 T3 ES 2084603T3 ES 89310697 T ES89310697 T ES 89310697T ES 89310697 T ES89310697 T ES 89310697T ES 2084603 T3 ES2084603 T3 ES 2084603T3
Authority
ES
Spain
Prior art keywords
developing
manufacture
low temperature
integrated circuits
temperature method
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89310697T
Other languages
English (en)
Inventor
Min-Liang Chen
Chung Wai Leung
Edward P Martin Jr
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
AT&T Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Inc filed Critical AT&T Inc
Application granted granted Critical
Publication of ES2084603T3 publication Critical patent/ES2084603T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC
    • H10P14/6923—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC the material being boron or phosphorus doped silicon oxides, e.g. BPSG, BSG or PSG
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof

Landscapes

  • Electrodes Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)

Abstract

EN UN METODO DE FABRICACION DE CIRCUITO INTEGRADO DE SEMICONDUCTOR, USO DE BORO Y FOSFORO CON ADITIVO TEOS (POR EJEMPLO, BPTEOS) DEBIDO A QUE UN PRIMER NIVEL DIELECTRICO PERMITE QUE EL DIELECTRICO CIRCULE A UNA TEMPERATURA MAXIMA DE 800 (POR) C. EN CONSECUENCIA, LA FUENTE TISI2 Y LOS CONTACTOS DE CONSUMO SE UTILICEN EN UN TRANSITOR DE EFECTO DE CAMPO SIN SUFRIR NUCLEACION Y AUMENTO DANDO POR RESULTADO AUMENTO DE TAMAÑO DEL GRANO, ASI RESISTENCIA AUMENTADA. UNA CAPA DE TEOS SE PUEDE DEPOSITAR ANTES QUE LA CAPA DE BPTEOS PARA IMPEDIR QUE LAS ESQUINAS VIVAS EN LA VALVULA DE COMPUERTA OCASIONEN POCA CONSISTENCIA Y POSIBLE ROTURA DE LA CAPA BPTEOS.
ES89310697T 1988-10-28 1989-10-18 Fabricacion de circuitos integrados, incluyendo metodo de baja temperatura para elaborar estructuras de siliciuro. Expired - Lifetime ES2084603T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US26448188A 1988-10-28 1988-10-28

Publications (1)

Publication Number Publication Date
ES2084603T3 true ES2084603T3 (es) 1996-05-16

Family

ID=23006256

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89310697T Expired - Lifetime ES2084603T3 (es) 1988-10-28 1989-10-18 Fabricacion de circuitos integrados, incluyendo metodo de baja temperatura para elaborar estructuras de siliciuro.

Country Status (5)

Country Link
EP (1) EP0366343B1 (es)
JP (1) JP2589829B2 (es)
DE (1) DE68926017T2 (es)
ES (1) ES2084603T3 (es)
HK (1) HK145996A (es)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5022958A (en) * 1990-06-27 1991-06-11 At&T Bell Laboratories Method of etching for integrated circuits with planarized dielectric
US5214305A (en) * 1990-08-28 1993-05-25 United Microelectronics Corporation Polycide gate MOSFET for integrated circuits
US5336640A (en) * 1991-01-28 1994-08-09 Kawasaki Steel Corporation Method of manufacturing a semiconductor device having an insulating layer composed of a BPSG film and a plasma-CVD silicon nitride film
JPH0582781A (ja) * 1991-09-24 1993-04-02 Nec Yamagata Ltd 半導体集積回路装置
US5418173A (en) * 1992-11-24 1995-05-23 At&T Corp. Method of reducing ionic contamination in integrated circuit fabrication
US7067442B1 (en) 1995-12-26 2006-06-27 Micron Technology, Inc. Method to avoid threshold voltage shift in thicker dielectric films
US6462394B1 (en) 1995-12-26 2002-10-08 Micron Technology, Inc. Device configured to avoid threshold voltage shift in a dielectric film
US5795820A (en) * 1996-07-01 1998-08-18 Advanced Micro Devices Method for simplifying the manufacture of an interlayer dielectric stack
JPH1167691A (ja) * 1997-08-22 1999-03-09 Sony Corp 半導体装置の製造方法

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6081833A (ja) * 1983-10-11 1985-05-09 Nec Corp 半導体装置
US4743564A (en) * 1984-12-28 1988-05-10 Kabushiki Kaisha Toshiba Method for manufacturing a complementary MOS type semiconductor device
JPS6225451A (ja) * 1985-07-25 1987-02-03 Toshiba Corp 相補型半導体装置の製造方法
JPS6337638A (ja) * 1986-07-31 1988-02-18 Fujitsu Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
EP0366343A2 (en) 1990-05-02
EP0366343B1 (en) 1996-03-20
DE68926017D1 (de) 1996-04-25
JP2589829B2 (ja) 1997-03-12
EP0366343A3 (en) 1990-08-29
HK145996A (en) 1996-08-09
JPH02170555A (ja) 1990-07-02
DE68926017T2 (de) 1996-08-22

Similar Documents

Publication Publication Date Title
SE7702444L (sv) Datorstyrt system for tillverkning av integrerade kretsar
JPS5324277A (en) Semiconductor devic e and its production
JPS52135685A (en) Semiconductor device
ES402164A1 (es) Un metodo para fabricar dispositivos monoliticos semicon- ductores.
JPS5582450A (en) Semiconductor integrated circuit
JPS5253673A (en) Device and production for semiconductor
JPS5214381A (en) Mis-type semiconductor device
JPS52109369A (en) Manufacture of semiconductor device
JPS648657A (en) Supplementary semiconductor integrated circuit device
JPS51149776A (en) Semiconductor device for power
JPS5339888A (en) Semiconductor integrated circuit device and its production
JPS6411362A (en) Semiconductor integrated circuit device
JPS522180A (en) Method of fabricating mos semiconductor integrated circuit
JPS5411687A (en) Manufacture for semiconductor integrated circuit
JPS5324280A (en) Production of semiconductor integrated circuit
JPS5329086A (en) Production of semiconductor device
JPS52141580A (en) Manufacture of mos-type semiconductor device
JPS5321568A (en) Production of semiconductor device
JPS5354987A (en) Complementary type mos semiconductor memory
JPS5368181A (en) Semiconductor integrated circuit
JPS5346287A (en) Production of semiconductor integrated circuit
JPS5582449A (en) Cell of master slice semiconductor integrated circuit
JPS5580332A (en) Semiconductor device
JPS5277680A (en) Semiconductor integrated circuit
JPS5372482A (en) Manufacture for semiconductor device

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 366343

Country of ref document: ES