ES2109222T3 - Circuito integrado cmos que tiene aislamiento mejorado. - Google Patents

Circuito integrado cmos que tiene aislamiento mejorado.

Info

Publication number
ES2109222T3
ES2109222T3 ES89308621T ES89308621T ES2109222T3 ES 2109222 T3 ES2109222 T3 ES 2109222T3 ES 89308621 T ES89308621 T ES 89308621T ES 89308621 T ES89308621 T ES 89308621T ES 2109222 T3 ES2109222 T3 ES 2109222T3
Authority
ES
Spain
Prior art keywords
type
cmos circuit
integrated cmos
boro
isolated
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES89308621T
Other languages
English (en)
Inventor
Min-Liang Chen
William T Cochran
Chung Wai Leung
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Inc
Original Assignee
AT&T Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&T Inc filed Critical AT&T Inc
Application granted granted Critical
Publication of ES2109222T3 publication Critical patent/ES2109222T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0123—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs
    • H10D84/0126—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs
    • H10D84/0165—Integrating together multiple components covered by H10D12/00 or H10D30/00, e.g. integrating multiple IGBTs the components including insulated gates, e.g. IGFETs the components including complementary IGFETs, e.g. CMOS devices
    • H10D84/0188—Manufacturing their isolation regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/01—Manufacture or treatment
    • H10W10/011—Manufacture or treatment of isolation regions comprising dielectric materials
    • H10W10/012—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS]
    • H10W10/0125—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics
    • H10W10/0126—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers
    • H10W10/0127—Manufacture or treatment of isolation regions comprising dielectric materials using local oxidation of silicon [LOCOS] comprising introducing electrical impurities in local oxidation regions, e.g. to alter LOCOS oxide growth characteristics introducing electrical active impurities in local oxidation regions to create channel stoppers using both n-type and p-type impurities, e.g. for isolation of complementary doped regions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/13—Isolation regions comprising dielectric materials formed using local oxidation of silicon [LOCOS], e.g. sealed interface localised oxidation [SILO] or side-wall mask isolation [SWAMI]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/80—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs
    • H10D84/82—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components
    • H10D84/83—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D12/00 or H10D30/00, e.g. integration of IGFETs of only field-effect components of only insulated-gate FETs [IGFET]
    • H10D84/85—Complementary IGFETs, e.g. CMOS
    • H10D84/859—Complementary IGFETs, e.g. CMOS comprising both N-type and P-type wells, e.g. twin-tub

Landscapes

  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Element Separation (AREA)

Abstract

SE AISLA UNA DEPRESION TIPO P EN UN CIRCUITO INTEGRADO CMOS QUEDA AISLADA DE LA DEPRESION ADYACENTE TIPO N MEDIANTE UN CAMPO DE OXIDO (65) CON UNA REGION DE SEPARACION (66) TIPO P FORMADA POR UN IMPLANTE DE IONES DE BORO. LA PERFORACION DE ESTE SE SELECCIONA PARA QUE LA CRESTA DE CONCENTRACION DE BORO ESTE SITUADA INMEDIATAMENTE DEBAJO DEL CAMPO DE OXIDO QUE ES CULTIVADA A CONTINUACION. ADEMAS, EL IMPLANTE PENETRA EN LAS REGIONES ACTIVAS PRODUCIENDO UNA CONCENTRACION DE BORO RETROGRADA EN LA REGION DEL CANAL N. ESTA TECNICA MEJORA SIMULTANEAMENTE EL AISLAMIENTO DEL DISPOSITIVO Y LAS CARACTERISTICAS DE PERFORACION DEL TRANSISTOR DE CANAL N, PERMITIENDO LA EXTENSION DE LA TECNOLOGIA CMOS A LAS GEOMETRIAS DE DISPOSITIVOS SUB-MICROMETRICAS.
ES89308621T 1988-08-30 1989-08-24 Circuito integrado cmos que tiene aislamiento mejorado. Expired - Lifetime ES2109222T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/238,362 US5045898A (en) 1988-08-30 1988-08-30 CMOS integrated circuit having improved isolation

Publications (1)

Publication Number Publication Date
ES2109222T3 true ES2109222T3 (es) 1998-01-16

Family

ID=22897539

Family Applications (1)

Application Number Title Priority Date Filing Date
ES89308621T Expired - Lifetime ES2109222T3 (es) 1988-08-30 1989-08-24 Circuito integrado cmos que tiene aislamiento mejorado.

Country Status (7)

Country Link
US (1) US5045898A (es)
EP (1) EP0357346B1 (es)
JP (1) JPH02112273A (es)
CA (1) CA1315419C (es)
DE (1) DE68928396T2 (es)
ES (1) ES2109222T3 (es)
HK (1) HK1004351A1 (es)

Families Citing this family (18)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2924395B2 (ja) * 1992-01-09 1999-07-26 日本電気株式会社 半導体装置の製造方法
US5344787A (en) * 1993-09-24 1994-09-06 Vlsi Technology, Inc. Latid implants for increasing the effective width of transistor elements in a semiconductor device
US5409848A (en) * 1994-03-31 1995-04-25 Vlsi Technology, Inc. Angled lateral pocket implants on p-type semiconductor devices
US7348227B1 (en) * 1995-03-23 2008-03-25 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and manufacturing method thereof
US5650350A (en) * 1995-08-11 1997-07-22 Micron Technology, Inc. Semiconductor processing method of forming a static random access memory cell and static random access memory cell
US20050036363A1 (en) * 1996-05-24 2005-02-17 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US7064376B2 (en) * 1996-05-24 2006-06-20 Jeng-Jye Shau High performance embedded semiconductor memory devices with multiple dimension first-level bit-lines
US5748547A (en) * 1996-05-24 1998-05-05 Shau; Jeng-Jye High performance semiconductor memory devices having multiple dimension bit lines
US5804497A (en) * 1996-08-07 1998-09-08 Advanced Micro Devices, Inc. Selectively doped channel region for increased IDsat and method for making same
US6083795A (en) * 1998-02-09 2000-07-04 Taiwan Semiconductor Manufacturing Company Large angle channel threshold implant for improving reverse narrow width effect
US6188106B1 (en) 1998-09-03 2001-02-13 Advanced Micro Devices, Inc. MOSFET having a highly doped channel liner and a dopant seal to provide enhanced device properties
US6362510B1 (en) 1998-12-07 2002-03-26 Advanced Micro Devices, Inc. Semiconductor topography having improved active device isolation and reduced dopant migration
US6144076A (en) * 1998-12-08 2000-11-07 Lsi Logic Corporation Well formation For CMOS devices integrated circuit structures
FR2794898B1 (fr) 1999-06-11 2001-09-14 France Telecom Dispositif semi-conducteur a tension de seuil compensee et procede de fabrication
US6812521B1 (en) 1999-11-16 2004-11-02 Advanced Micro Devices, Inc. Method and apparatus for improved performance of flash memory cell devices
US9401274B2 (en) 2013-08-09 2016-07-26 Taiwan Semiconductor Manufacturing Company Limited Methods and systems for dopant activation using microwave radiation
FI127168B (en) 2014-05-20 2017-12-29 Murata Manufacturing Co Method for making a MEMS structure and use of the method
DE102015106397B4 (de) * 2015-04-16 2019-08-22 Taiwan Semiconductor Manufacturing Company, Ltd. Verfahren und Systeme zur Dotierstoffaktivierung mithilfe von Mikrowellenbestrahlung

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5379474A (en) * 1976-12-24 1978-07-13 Matsushita Electric Ind Co Ltd Manufacture of semiconductor device
US4354307A (en) * 1979-12-03 1982-10-19 Burroughs Corporation Method for mass producing miniature field effect transistors in high density LSI/VLSI chips
JPS5965481A (ja) * 1982-10-06 1984-04-13 Nec Corp 半導体装置
DE3314450A1 (de) 1983-04-21 1984-10-25 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von hochintegrierten komplementaeren mos-feldeffekttransistorschaltungen
DE3467953D1 (en) * 1983-04-21 1988-01-14 Toshiba Kk Semiconductor device having an element isolation layer and method of manufacturing the same
US4471523A (en) 1983-05-02 1984-09-18 International Business Machines Corporation Self-aligned field implant for oxide-isolated CMOS FET
JPS5925242A (ja) * 1983-07-11 1984-02-09 Hitachi Ltd 半導体装置
US4554726A (en) * 1984-04-17 1985-11-26 At&T Bell Laboratories CMOS Integrated circuit technology utilizing dual implantation of slow and fast diffusing donor ions to form the n-well
JPS61159766A (ja) * 1984-12-31 1986-07-19 Sony Corp 半導体装置の製造方法
WO1987005443A1 (en) * 1986-03-04 1987-09-11 Motorola, Inc. High/low doping profile for twin well process
US4889825A (en) * 1986-03-04 1989-12-26 Motorola, Inc. High/low doping profile for twin well process
US4903107A (en) * 1986-12-29 1990-02-20 General Electric Company Buried oxide field isolation structure with composite dielectric
DE69526976T2 (de) 1995-07-26 2003-01-16 Surefire, Llc Handwaffetragevorrichtung

Also Published As

Publication number Publication date
EP0357346B1 (en) 1997-10-22
DE68928396T2 (de) 1998-02-19
JPH02112273A (ja) 1990-04-24
CA1315419C (en) 1993-03-30
EP0357346A3 (en) 1991-09-25
EP0357346A2 (en) 1990-03-07
US5045898A (en) 1991-09-03
DE68928396D1 (de) 1997-11-27
HK1004351A1 (en) 1998-11-20

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