ES2150972T3 - Dispositivo para justificar a intervalos regulares un tren numerico. - Google Patents

Dispositivo para justificar a intervalos regulares un tren numerico.

Info

Publication number
ES2150972T3
ES2150972T3 ES94402338T ES94402338T ES2150972T3 ES 2150972 T3 ES2150972 T3 ES 2150972T3 ES 94402338 T ES94402338 T ES 94402338T ES 94402338 T ES94402338 T ES 94402338T ES 2150972 T3 ES2150972 T3 ES 2150972T3
Authority
ES
Spain
Prior art keywords
buffer memory
link
regular intervals
synchronous
value
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES94402338T
Other languages
English (en)
Inventor
Jean-Paul Etienne
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Alcatel Lucent SAS
Nokia Inc
Original Assignee
Alcatel SA
Nokia Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Alcatel SA, Nokia Inc filed Critical Alcatel SA
Application granted granted Critical
Publication of ES2150972T3 publication Critical patent/ES2150972T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04J—MULTIPLEX COMMUNICATION
    • H04J3/00—Time-division multiplex systems
    • H04J3/02—Details
    • H04J3/06—Synchronising arrangements
    • H04J3/07—Synchronising arrangements using pulse stuffing for systems with different or fluctuating information rates or bit rates
    • H04J3/076—Bit and byte stuffing, e.g. SDH/PDH desynchronisers, bit-leaking

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Synchronisation In Digital Transmission Systems (AREA)
  • Time-Division Multiplex Systems (AREA)
  • Analogue/Digital Conversion (AREA)
  • Control Of Stepping Motors (AREA)
  • Train Traffic Observation, Control, And Security (AREA)

Abstract

ESTE DISPOSITIVO JUSTIFICA A INTERVALOS REGULARES UN TREN DIGITAL CONSTITUIDO DE HILERAS DE BITS PROCEDENTES DE UN PRIMER ENLACE SINCRONO (1) ACOMPASADO POR UN PRIMER RELOJ (HE) Y QUE HA DE SER EMITIDO SOBRE UN SEGUNDO ENLACE SINCRONO (10) ACOMPASADO POR UN SEGUNDO RELOJ (HL). COMPRENDE: MEDIA (5); ESCRITURA A LA MEMORIA INTERMEDIA; ORCIONA UNA DIRECCION DE LECTURA A LA MEMORIA INTERMEDIA; MEDIOS (12, 13) PARA CALCULAR EL VALOR DEL LLENADO (DELTAP) DE LA MEMORIA INTERMEDIA (5); ALOR (DELTAP) CON UN PRIMER Y UN SEGUNDO VALOR DE UMBRAL (NF, NE), Y PARA PRODUCIR UNA SEÑAL DE CONTROL DE JUSTIFICACION (JP, JN); ENTO DE UNA HILERA EMITIDA AL MISMO TIEMPO SOBRE LA SEGUNDA CONEXION (10). APLICACION EN LAS PASARELAS EN LA ENTRADA Y EN LAS REDES DE TELECOMUNICACION QUE UTILIZAN LA JERARQUIA DIGITAL SINCRONA.
ES94402338T 1993-10-20 1994-10-18 Dispositivo para justificar a intervalos regulares un tren numerico. Expired - Lifetime ES2150972T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9312497A FR2711435B1 (fr) 1993-10-20 1993-10-20 Dispositif pour justifier à intervalles réguliers un train numérique.

Publications (1)

Publication Number Publication Date
ES2150972T3 true ES2150972T3 (es) 2000-12-16

Family

ID=9452032

Family Applications (1)

Application Number Title Priority Date Filing Date
ES94402338T Expired - Lifetime ES2150972T3 (es) 1993-10-20 1994-10-18 Dispositivo para justificar a intervalos regulares un tren numerico.

Country Status (7)

Country Link
US (1) US5621775A (es)
EP (1) EP0650273B1 (es)
AT (1) ATE196580T1 (es)
AU (1) AU683490B2 (es)
DE (1) DE69425938T2 (es)
ES (1) ES2150972T3 (es)
FR (1) FR2711435B1 (es)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5822383A (en) * 1995-12-15 1998-10-13 Cisco Technology, Inc. System and method for maintaining network synchronization utilizing digital phase comparison techniques with synchronous residual time stamps
US5761203A (en) * 1996-04-04 1998-06-02 Lucent Technologies Inc. Synchronous and asynchronous recovery of signals in an ATM network
US6064706A (en) * 1996-05-01 2000-05-16 Alcatel Usa, Inc. Apparatus and method of desynchronizing synchronously mapped asynchronous data
DE19730716A1 (de) * 1996-10-21 1998-04-23 Fraunhofer Ges Forschung Triggerung eines Meßverfahrens zur Qualitätsbeurteilung von Audio- und/oder Sprachsignalen
US6636518B1 (en) * 1996-12-16 2003-10-21 Juniper Networks Synchronizing source-synchronous links in a switching device
US6269136B1 (en) * 1998-02-02 2001-07-31 Microunity Systems Engineering, Inc. Digital differential analyzer data synchronizer
EP0993644A2 (en) * 1998-04-30 2000-04-19 Koninklijke Philips Electronics N.V. Transcoding of a data stream
FI982040A7 (fi) * 1998-09-22 2000-03-23 Nokia Multimedia Network Terminals Oy Menetelmä ja laite datavirran synkronoimiseksi
US6229863B1 (en) 1998-11-02 2001-05-08 Adc Telecommunications, Inc. Reducing waiting time jitter
US6980569B1 (en) 1999-10-18 2005-12-27 Siemens Communications, Inc. Apparatus and method for optimizing packet length in ToL networks
US6747999B1 (en) 1999-11-15 2004-06-08 Siemens Information And Communication Networks, Inc. Jitter buffer adjustment algorithm
US6683889B1 (en) 1999-11-15 2004-01-27 Siemens Information & Communication Networks, Inc. Apparatus and method for adaptive jitter buffers
GB9930849D0 (en) * 1999-12-24 2000-02-16 Koninkl Philips Electronics Nv Data communications
KR100861884B1 (ko) * 2000-06-20 2008-10-09 코닌클리케 필립스 일렉트로닉스 엔.브이. 정현파 코딩 방법 및 장치
US7143157B2 (en) * 2002-03-25 2006-11-28 Hewlett-Packard Development Company, L.P. Managing the network impact of a digital transmitter
US7984209B1 (en) * 2006-12-12 2011-07-19 Altera Corporation Data interface methods and circuitry with reduced latency
US8681917B2 (en) 2010-03-31 2014-03-25 Andrew Llc Synchronous transfer of streaming data in a distributed antenna system

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4791652A (en) * 1987-06-04 1988-12-13 Northern Telecom Limited Synchronization of asynchronous data signals
US5331641A (en) * 1990-07-27 1994-07-19 Transwitch Corp. Methods and apparatus for retiming and realignment of STS-1 signals into STS-3 type signal
DE4101270A1 (de) * 1991-01-17 1992-07-23 Siemens Ag Verfahren zur uebertragung von digitalsignalen
JPH05183530A (ja) * 1991-06-06 1993-07-23 Fujitsu Ltd 同期ペイロードポインタ処理方式

Also Published As

Publication number Publication date
FR2711435B1 (fr) 1995-12-29
AU7570994A (en) 1995-05-11
AU683490B2 (en) 1997-11-13
US5621775A (en) 1997-04-15
EP0650273A1 (fr) 1995-04-26
EP0650273B1 (fr) 2000-09-20
FR2711435A1 (fr) 1995-04-28
DE69425938D1 (de) 2000-10-26
DE69425938T2 (de) 2001-05-03
ATE196580T1 (de) 2000-10-15

Similar Documents

Publication Publication Date Title
ES2150972T3 (es) Dispositivo para justificar a intervalos regulares un tren numerico.
US5142529A (en) Method and means for transferring a data payload from a first SONET signal to a SONET signal of different frequency
JP2563691B2 (ja) ディジタル信号同期装置
US20100265953A1 (en) Method and apparatus for signal splitting and combining
US5835543A (en) Digital desynchronizer
JPH0779210A (ja) 伝送システム
JPH06244827A (ja) ２つの信号のビットレートを適合調整するための回路装置
US5777998A (en) Method and circuit arrangement for the realization of the higher path adaptation/mapping function in synchronous digital hierarchy/optical network equipment
US5214643A (en) Method for inserting an asynchronous 139,264 kbit/s signal into a 155,520 kbit/s signal
US5802122A (en) Transmission system comprising a matching circuit
US4885746A (en) Frequency converter
JPH0671258B2 (ja) 情報伝送処理装置
JP2005516530A5 (es)
GB2128450A (en) Time-division switching unit
CA2520906C (en) Method and apparatus for frame alignment
US4669080A (en) Synchronizing circuit in a plesiochronous digital signal multiplexer
JPH0761056B2 (ja) 特定フレーム構造体への情報ビットの挿入装置
US20040037182A1 (en) Phase adjusting apparatus, phase adjusting method for use therein, and program for phase adjusting method
JP2630228B2 (ja) Ｓｏｎｅｔ／ｓｄｈフレーム変換方法および回路
US5383189A (en) Method and circuit for demultiplexing digital signals capable of asborbing destuffing jitter
RU2000102643A (ru) Способ и устройство для адаптации и коммутации потока данных
KR100301294B1 (ko) 광전송 시스템의 바이트단위 데이터처리 장치
JP2867943B2 (ja) Ｓｄｈ伝送システムの遅延変動吸収方法
KR100325133B1 (ko) 에이유4 프레임의 씨4 데이터를 이4 데이터로 변환하는 회로
ITTO990679A1 (it) Metodo di mappatura di flussi tributari in trame a divisione di tempoin reti di telecomunicazioni e relativo circuito.

Legal Events

Date Code Title Description
FG2A Definitive protection

Ref document number: 650273

Country of ref document: ES