ES440909A0 - Procedimiento para realizar transistores complementarios monoliticos en un substrato tipo p de elevada resistividad. - Google Patents

Procedimiento para realizar transistores complementarios monoliticos en un substrato tipo p de elevada resistividad.

Info

Publication number
ES440909A0
ES440909A0 ES440909A ES440909A ES440909A0 ES 440909 A0 ES440909 A0 ES 440909A0 ES 440909 A ES440909 A ES 440909A ES 440909 A ES440909 A ES 440909A ES 440909 A0 ES440909 A0 ES 440909A0
Authority
ES
Spain
Prior art keywords
procedure
high resistivity
substrate type
complementary transistors
make monolithic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
ES440909A
Other languages
English (en)
Spanish (es)
Inventor
William Edgar Beadle
Stanley Floyd Moyer
Aristides Antony Yiannoulos
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&T Corp
Original Assignee
Western Electric Co Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Western Electric Co Inc filed Critical Western Electric Co Inc
Publication of ES440909A0 publication Critical patent/ES440909A0/es
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/67—Complementary BJTs
    • H10D84/673—Vertical complementary BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0119—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs
    • H10D84/0121—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including complementary BJTs the complementary BJTs being vertical BJTs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
ES440909A 1974-09-19 1976-01-23 Procedimiento para realizar transistores complementarios monoliticos en un substrato tipo p de elevada resistividad. Pending ES440909A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US50757074A 1974-09-19 1974-09-19

Publications (1)

Publication Number Publication Date
ES440909A0 true ES440909A0 (es) 1977-03-16

Family

ID=24019174

Family Applications (1)

Application Number Title Priority Date Filing Date
ES440909A Pending ES440909A0 (es) 1974-09-19 1976-01-23 Procedimiento para realizar transistores complementarios monoliticos en un substrato tipo p de elevada resistividad.

Country Status (10)

Country Link
JP (1) JPS5157172A (fr)
BE (1) BE833455A (fr)
CA (1) CA1038968A (fr)
DE (1) DE2541161A1 (fr)
ES (1) ES440909A0 (fr)
FR (1) FR2285717A1 (fr)
GB (1) GB1525247A (fr)
IT (1) IT1042581B (fr)
NL (1) NL7510994A (fr)
SE (1) SE403214B (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55143064A (en) * 1979-04-24 1980-11-08 Nec Corp Semiconductor device
JPS57106046A (en) * 1980-12-23 1982-07-01 Toshiba Corp Manufacture of semiconductor device
JPH0713969B2 (ja) * 1986-01-13 1995-02-15 三洋電機株式会社 縦型ｐｎｐトランジスタ
GB2186117B (en) * 1986-01-30 1989-11-01 Sgs Microelettronica Spa Monolithically integrated semiconductor device containing bipolar junction,cmosand dmos transistors and low leakage diodes and a method for its fabrication
EP0347550A3 (fr) * 1988-06-21 1991-08-28 Texas Instruments Incorporated Procédé pour l'intégration de transistors bipolaires isolés verticaux et à grand bêta

Also Published As

Publication number Publication date
JPS5157172A (fr) 1976-05-19
IT1042581B (it) 1980-01-30
FR2285717B1 (fr) 1980-04-30
SE403214B (sv) 1978-07-31
GB1525247A (en) 1978-09-20
SE7510075L (sv) 1976-03-22
CA1038968A (fr) 1978-09-19
BE833455A (fr) 1976-01-16
DE2541161A1 (de) 1976-04-01
NL7510994A (nl) 1976-03-23
FR2285717A1 (fr) 1976-04-16

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