ES8404111A1 - Perfeccionamientos en una unidad de base para conjuntos de compuertas logicas de circuito integrado. - Google Patents

Perfeccionamientos en una unidad de base para conjuntos de compuertas logicas de circuito integrado.

Info

Publication number
ES8404111A1
ES8404111A1 ES521503A ES521503A ES8404111A1 ES 8404111 A1 ES8404111 A1 ES 8404111A1 ES 521503 A ES521503 A ES 521503A ES 521503 A ES521503 A ES 521503A ES 8404111 A1 ES8404111 A1 ES 8404111A1
Authority
ES
Spain
Prior art keywords
integrated circuit
base unit
circuit logic
logic gate
type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
ES521503A
Other languages
English (en)
Other versions
ES521503A0 (es
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Telecom Italia SpA
Original Assignee
CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by CSELT Centro Studi e Laboratori Telecomunicazioni SpA filed Critical CSELT Centro Studi e Laboratori Telecomunicazioni SpA
Publication of ES8404111A1 publication Critical patent/ES8404111A1/es
Publication of ES521503A0 publication Critical patent/ES521503A0/es
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/90—Masterslice integrated circuits
    • H10D84/903—Masterslice integrated circuits comprising field effect technology
    • H10D84/907—CMOS gate arrays
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S257/00—Active solid-state devices, e.g. transistors, solid-state diodes
    • Y10S257/923—Active solid-state devices, e.g. transistors, solid-state diodes with means to optimize electrical conductor current carrying capacity, e.g. particular conductor aspect ratio

Landscapes

  • Design And Manufacture Of Integrated Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Logic Circuits (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

UNIDAD DE BASE PARA CONJUNTOS DE COMPUERTAS LOGICAS DE CIRCUITO INTEGRADO.CONSTA DE DOS TRANSISTORES DE EFECTO DE CAMPO DE TIPO Y Y DE DOS TRANSISTORES DE EFECTO DE CAMPO DE TIPO N, REALIZADOS DE MANERA QUE LOS TRANSISTORES DE UN MISMO TIPO TENGAN EN COMUN UNO DE LOS ELECTRODOS PUESTOS EN LAS EXTREMIDADES DEL CANAL. LAS PUERTAS DE UN TRANSISTOR DE TIPO P Y DE UN TRANSISTOR DE TIPO N, SIMETRICOS RESPECTO DE UN PUNTO CENTRAL DE LA UNIDAD, ESTAN CONECTADAS POR UNA PRIMERA INTERCONEXION DE POLISILICIO QUE ATRAVIESA DOS METALIZACIONES PARALELAS RELATIVAS A LAS ALIMENTACIONES,SIENDO ESTAS METALIZACIONES ATRAVESADAS TAMBIEN POR UNA SEGUNDA INTERCONEXION DE POLISILICIO QUE UNE AREAS DISPUESTAS EN LOS LADOS OPUESTOS DE UNA ZONA DELIMITADA POR LAS ALIMENTACIONES.
ES521503A 1982-04-15 1983-04-15 Perfeccionamientos en una unidad de base para conjuntos de compuertas logicas de circuito integrado. Granted ES521503A0 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IT67501/82A IT1191188B (it) 1982-04-15 1982-04-15 Cella elementare per reti di porte logiche a circuito integrato

Publications (2)

Publication Number Publication Date
ES8404111A1 true ES8404111A1 (es) 1984-04-01
ES521503A0 ES521503A0 (es) 1984-04-01

Family

ID=11302946

Family Applications (1)

Application Number Title Priority Date Filing Date
ES521503A Granted ES521503A0 (es) 1982-04-15 1983-04-15 Perfeccionamientos en una unidad de base para conjuntos de compuertas logicas de circuito integrado.

Country Status (10)

Country Link
US (1) US4595940A (es)
EP (1) EP0092176B1 (es)
JP (1) JPS59938A (es)
AT (1) ATE36207T1 (es)
CA (1) CA1187624A (es)
DE (2) DE92176T1 (es)
DK (1) DK162867C (es)
ES (1) ES521503A0 (es)
IT (1) IT1191188B (es)
NO (1) NO164947C (es)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4783749A (en) * 1985-05-21 1988-11-08 Siemens Aktiengesellschaft Basic cell realized in the CMOS technique and a method for the automatic generation of such a basic cell
DE4002780C2 (de) * 1990-01-31 1995-01-19 Fraunhofer Ges Forschung Basiszelle für eine kanallose Gate-Array-Anordnung
US5291043A (en) * 1990-02-07 1994-03-01 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having gate array
US6399972B1 (en) * 2000-03-13 2002-06-04 Oki Electric Industry Co., Ltd. Cell based integrated circuit and unit cell architecture therefor
JP2011242541A (ja) * 2010-05-17 2011-12-01 Panasonic Corp 半導体集積回路装置、および標準セルの端子構造
CA2819268C (en) 2010-12-20 2017-10-17 The Nielsen Company (Us), Llc Methods and apparatus to determine media impressions using distributed demographic information
AU2013204865B2 (en) 2012-06-11 2015-07-09 The Nielsen Company (Us), Llc Methods and apparatus to share online media impressions data

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1440512A (en) * 1973-04-30 1976-06-23 Rca Corp Universal array using complementary transistors
JPS5925381B2 (ja) * 1977-12-30 1984-06-16 富士通株式会社 半導体集積回路装置
US4356504A (en) * 1980-03-28 1982-10-26 International Microcircuits, Inc. MOS Integrated circuit structure for discretionary interconnection
JPS5749253A (en) * 1980-09-09 1982-03-23 Toshiba Corp Semiconductor integrated circuit

Also Published As

Publication number Publication date
NO164947C (no) 1990-11-28
DE3377603D1 (en) 1988-09-08
DK158383D0 (da) 1983-04-11
ATE36207T1 (de) 1988-08-15
NO164947B (no) 1990-08-20
JPS59938A (ja) 1984-01-06
EP0092176B1 (en) 1988-08-03
DK162867C (da) 1992-05-04
JPH0254670B2 (es) 1990-11-22
IT8267501A1 (it) 1983-10-15
IT8267501A0 (it) 1982-04-15
US4595940A (en) 1986-06-17
IT1191188B (it) 1988-02-24
CA1187624A (en) 1985-05-21
ES521503A0 (es) 1984-04-01
DE92176T1 (de) 1985-10-24
EP0092176A2 (en) 1983-10-26
DK162867B (da) 1991-12-16
NO831320L (no) 1983-10-17
DK158383A (da) 1983-10-16
EP0092176A3 (en) 1985-08-21

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Legal Events

Date Code Title Description
FD1A Patent lapsed

Effective date: 19991108