FR2879800B1 - Dispositif a memoire integree et procede - Google Patents

Dispositif a memoire integree et procede

Info

Publication number
FR2879800B1
FR2879800B1 FR0507831A FR0507831A FR2879800B1 FR 2879800 B1 FR2879800 B1 FR 2879800B1 FR 0507831 A FR0507831 A FR 0507831A FR 0507831 A FR0507831 A FR 0507831A FR 2879800 B1 FR2879800 B1 FR 2879800B1
Authority
FR
France
Prior art keywords
memory device
integrated memory
integrated
memory
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR0507831A
Other languages
English (en)
Other versions
FR2879800A1 (fr
Inventor
Ronald Kakoschke
Thomas Nirschl
Klaus Schrufer
Danny Pak Chum Shum
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Infineon Technologies AG
Original Assignee
Infineon Technologies AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Infineon Technologies AG filed Critical Infineon Technologies AG
Publication of FR2879800A1 publication Critical patent/FR2879800A1/fr
Application granted granted Critical
Publication of FR2879800B1 publication Critical patent/FR2879800B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/04Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0416Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and no select transistor, e.g. UV EPROM
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D48/00Individual devices not covered by groups H10D1/00 - H10D44/00
    • H10D48/30Devices controlled by electric currents or voltages
    • H10D48/32Devices controlled by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H10D48/34Bipolar devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10BELECTRONIC MEMORY DEVICES
    • H10B69/00Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10DINORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D8/00Diodes
    • H10D8/812Charge-trapping diodes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Semiconductor Memories (AREA)
  • Non-Volatile Memory (AREA)
  • Mram Or Spin Memory Techniques (AREA)
FR0507831A 2004-08-13 2005-07-22 Dispositif a memoire integree et procede Expired - Fee Related FR2879800B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/918,335 US8288813B2 (en) 2004-08-13 2004-08-13 Integrated memory device having columns having multiple bit lines

Publications (2)

Publication Number Publication Date
FR2879800A1 FR2879800A1 (fr) 2006-06-23
FR2879800B1 true FR2879800B1 (fr) 2015-05-29

Family

ID=34862261

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0507831A Expired - Fee Related FR2879800B1 (fr) 2004-08-13 2005-07-22 Dispositif a memoire integree et procede

Country Status (6)

Country Link
US (2) US8288813B2 (fr)
JP (1) JP4571544B2 (fr)
CN (1) CN1750170B (fr)
DE (1) DE102005029493B4 (fr)
FR (1) FR2879800B1 (fr)
GB (1) GB2417131B (fr)

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US7359226B2 (en) 2006-08-28 2008-04-15 Qimonda Ag Transistor, memory cell array and method for forming and operating a memory device
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US8173993B2 (en) * 2009-12-04 2012-05-08 International Business Machines Corporation Gate-all-around nanowire tunnel field effect transistors
US8129247B2 (en) * 2009-12-04 2012-03-06 International Business Machines Corporation Omega shaped nanowire field effect transistors
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US8097515B2 (en) * 2009-12-04 2012-01-17 International Business Machines Corporation Self-aligned contacts for nanowire field effect transistors
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CN102456745B (zh) * 2010-10-22 2013-09-04 北京大学 一种快闪存储器及其制备方法和操作方法
CN102738244B (zh) * 2011-04-08 2015-07-29 北京大学 一种sonos快闪存储器及其制备方法和操作方法
CN102738169A (zh) * 2011-04-13 2012-10-17 北京大学 一种快闪存储器及其制备方法
CN102354694A (zh) * 2011-08-25 2012-02-15 复旦大学 一种自对准的垂直式非挥发性半导体存储器件
CN103022040B (zh) * 2011-09-28 2015-12-02 无锡华润上华科技有限公司 只读存储器及其制作方法
JP5743831B2 (ja) * 2011-09-29 2015-07-01 株式会社東芝 半導体装置
CN103137626A (zh) * 2011-11-29 2013-06-05 中国科学院微电子研究所 一种平面浮栅闪存器件及其制备方法
US9356158B2 (en) 2012-07-20 2016-05-31 Semiconductor Components Industries, Llc Electronic device including a tunnel structure
JP2014203851A (ja) 2013-04-01 2014-10-27 株式会社東芝 半導体装置及びその製造方法
CN103247626A (zh) 2013-05-02 2013-08-14 复旦大学 一种半浮栅器件及其制造方法
CN103594376B (zh) * 2013-11-08 2016-02-17 北京大学 一种结调制型隧穿场效应晶体管及其制备方法
US9391162B2 (en) * 2014-04-04 2016-07-12 Taiwan Semiconductor Manufacturing Company, Ltd. Tunnel MOSFET with ferroelectric gate stack
US9397176B2 (en) * 2014-07-30 2016-07-19 Freescale Semiconductor, Inc. Method of forming split gate memory with improved reliability
JP6872132B2 (ja) 2016-03-07 2021-05-19 ソニーグループ株式会社 半導体記憶素子、半導体装置、電子機器、および半導体記憶素子の製造方法
KR102638610B1 (ko) * 2017-01-11 2024-02-22 삼성전자주식회사 자기 메모리 장치
JP7016177B2 (ja) * 2017-09-29 2022-02-04 国立研究開発法人産業技術総合研究所 半導体装置
US11222970B2 (en) * 2017-12-28 2022-01-11 Integrated Silicon Solution, (Cayman) Inc. Perpendicular magnetic tunnel junction memory cells having vertical channels
US10658425B2 (en) 2017-12-28 2020-05-19 Spin Memory, Inc. Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
US10468293B2 (en) 2017-12-28 2019-11-05 Spin Memory, Inc. Methods of forming perpendicular magnetic tunnel junction memory cells having vertical channels
US10460778B2 (en) 2017-12-29 2019-10-29 Spin Memory, Inc. Perpendicular magnetic tunnel junction memory cells having shared source contacts
CN108417575A (zh) * 2018-03-14 2018-08-17 上海华虹宏力半导体制造有限公司 闪存单元、闪存阵列及其操作方法
CN111223868A (zh) * 2018-11-27 2020-06-02 钰成投资股份有限公司 半导体非挥发性存储元件结构
CN112349322A (zh) * 2019-08-06 2021-02-09 上海磁宇信息科技有限公司 磁性随机存储器架构及其制造方法
US11581334B2 (en) * 2021-02-05 2023-02-14 Taiwan Semiconductor Manufacturing Company, Ltd. Cocktail layer over gate dielectric layer of FET FeRAM
US20220302129A1 (en) * 2021-03-10 2022-09-22 Invention And Collaboration Laboratory Pte. Ltd. SRAM Cell Structures

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Also Published As

Publication number Publication date
CN1750170B (zh) 2013-06-05
GB0513538D0 (en) 2005-08-10
DE102005029493B4 (de) 2014-10-16
GB2417131B (en) 2006-10-11
GB2417131A (en) 2006-02-15
DE102005029493A1 (de) 2006-02-23
CN1750170A (zh) 2006-03-22
US20060033145A1 (en) 2006-02-16
US20110171803A1 (en) 2011-07-14
US8389357B2 (en) 2013-03-05
US8288813B2 (en) 2012-10-16
JP2006054435A (ja) 2006-02-23
FR2879800A1 (fr) 2006-06-23
JP4571544B2 (ja) 2010-10-27

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