FR2935536B1 - Procede de detourage progressif - Google Patents

Procede de detourage progressif

Info

Publication number
FR2935536B1
FR2935536B1 FR0855875A FR0855875A FR2935536B1 FR 2935536 B1 FR2935536 B1 FR 2935536B1 FR 0855875 A FR0855875 A FR 0855875A FR 0855875 A FR0855875 A FR 0855875A FR 2935536 B1 FR2935536 B1 FR 2935536B1
Authority
FR
France
Prior art keywords
progressive
detouring method
detouring
progressive detouring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0855875A
Other languages
English (en)
Other versions
FR2935536A1 (fr
Inventor
Marcel Broekaart
Marion Migette
Sebastien Molinari
Eric Neyret
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Soitec SA
Original Assignee
Soitec SA
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority to FR0855875A priority Critical patent/FR2935536B1/fr
Application filed by Soitec SA filed Critical Soitec SA
Priority to JP2011511037A priority patent/JP5319764B2/ja
Priority to EP09811094.3A priority patent/EP2324491B1/fr
Priority to PCT/EP2009/059961 priority patent/WO2010026007A1/fr
Priority to KR1020107022381A priority patent/KR101160316B1/ko
Priority to US12/934,026 priority patent/US8679944B2/en
Priority to CN200980115233.3A priority patent/CN102017092B/zh
Priority to TW098128553A priority patent/TWI443730B/zh
Publication of FR2935536A1 publication Critical patent/FR2935536A1/fr
Application granted granted Critical
Publication of FR2935536B1 publication Critical patent/FR2935536B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P52/00—Grinding, lapping or polishing of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P90/00—Preparation of wafers not covered by a single main group of this subclass, e.g. wafer reinforcement
    • H10P90/19—Preparing inhomogeneous wafers
    • H10P90/1904—Preparing vertically inhomogeneous wafers
    • H10P90/1906—Preparing SOI wafers
    • H10P90/1922—Preparing SOI wafers using silicon etch back techniques, e.g. BESOI or ELTRAN
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W10/00—Isolation regions in semiconductor bodies between components of integrated devices
    • H10W10/10—Isolation regions comprising dielectric materials
    • H10W10/181—Semiconductor-on-insulator [SOI] isolation regions, e.g. buried oxide regions of SOI wafers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
    • H10W90/722—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between stacked chips
FR0855875A 2008-09-02 2008-09-02 Procede de detourage progressif Active FR2935536B1 (fr)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FR0855875A FR2935536B1 (fr) 2008-09-02 2008-09-02 Procede de detourage progressif
EP09811094.3A EP2324491B1 (fr) 2008-09-02 2009-07-31 Procédé de finition progressive
PCT/EP2009/059961 WO2010026007A1 (fr) 2008-09-02 2009-07-31 Procédé de finition progressive
KR1020107022381A KR101160316B1 (ko) 2008-09-02 2009-07-31 점진적인 트리밍 방법
JP2011511037A JP5319764B2 (ja) 2008-09-02 2009-07-31 漸進トリミング法
US12/934,026 US8679944B2 (en) 2008-09-02 2009-07-31 Progressive trimming method
CN200980115233.3A CN102017092B (zh) 2008-09-02 2009-07-31 顺序冲切方法
TW098128553A TWI443730B (zh) 2008-09-02 2009-08-25 一漸近式修整方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR0855875A FR2935536B1 (fr) 2008-09-02 2008-09-02 Procede de detourage progressif

Publications (2)

Publication Number Publication Date
FR2935536A1 FR2935536A1 (fr) 2010-03-05
FR2935536B1 true FR2935536B1 (fr) 2010-09-24

Family

ID=40409956

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0855875A Active FR2935536B1 (fr) 2008-09-02 2008-09-02 Procede de detourage progressif

Country Status (8)

Country Link
US (1) US8679944B2 (fr)
EP (1) EP2324491B1 (fr)
JP (1) JP5319764B2 (fr)
KR (1) KR101160316B1 (fr)
CN (1) CN102017092B (fr)
FR (1) FR2935536B1 (fr)
TW (1) TWI443730B (fr)
WO (1) WO2010026007A1 (fr)

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FR2962141A1 (fr) * 2010-06-30 2012-01-06 Soitec Silicon On Insulator Technologies Procédé de désoxydation d'une structure multicouche a l'acide fluorhydrique
US8338266B2 (en) 2010-08-11 2012-12-25 Soitec Method for molecular adhesion bonding at low pressure
FR2964193A1 (fr) 2010-08-24 2012-03-02 Soitec Silicon On Insulator Procede de mesure d'une energie d'adhesion, et substrats associes
JP5279775B2 (ja) * 2010-08-25 2013-09-04 株式会社東芝 半導体装置の製造方法
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KR102524962B1 (ko) * 2016-11-14 2023-04-21 삼성전자주식회사 기판 구조체 제조 방법 및 이를 이용하여 제조된 기판 구조체
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JP6890495B2 (ja) * 2017-07-26 2021-06-18 株式会社ディスコ ウェーハの加工方法
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CN109786234B (zh) * 2017-11-13 2021-06-04 中芯国际集成电路制造(上海)有限公司 一种半导体器件的制造方法
JP6879223B2 (ja) * 2018-01-18 2021-06-02 株式会社Sumco 貼り合わせウェーハの製造方法
JP7237464B2 (ja) * 2018-05-24 2023-03-13 キオクシア株式会社 半導体装置の製造方法
JP7258489B2 (ja) 2018-08-21 2023-04-17 株式会社岡本工作機械製作所 半導体装置の製造方法及び製造装置
CN110943066A (zh) * 2018-09-21 2020-03-31 联华电子股份有限公司 具有高电阻晶片的半导体结构及高电阻晶片的接合方法
JP7237557B2 (ja) * 2018-12-14 2023-03-13 株式会社東京精密 貼り合わせウェーハのエッジトリミング加工方法
CN110189985B (zh) 2019-06-19 2020-10-30 武汉新芯集成电路制造有限公司 一种键合结构及其制造方法
CN110459555A (zh) * 2019-08-29 2019-11-15 长春长光圆辰微电子技术有限公司 背照式图像传感器晶圆边缘无硅膜缺陷的工艺制程方法
CN110854011A (zh) * 2019-09-30 2020-02-28 芯盟科技有限公司 堆叠键合晶圆的处理方法
JP7313775B2 (ja) * 2019-10-18 2023-07-25 株式会社ディスコ ウェーハの加工方法
JP7436187B2 (ja) * 2019-11-25 2024-02-21 株式会社ディスコ ウエーハの加工方法
CN111015815B (zh) * 2019-12-30 2021-08-10 苏州科阳光电科技有限公司 一种多层复合材料的切割方法
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FR3120985B1 (fr) * 2021-03-19 2023-03-31 Soitec Silicon On Insulator Procédé de fabrication d’une hétérostructure
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TWI918066B (zh) 2024-08-08 2026-03-11 合晶科技股份有限公司 半導體基板及其製造方法
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JP2011524083A (ja) 2011-08-25
US20110097874A1 (en) 2011-04-28
WO2010026007A1 (fr) 2010-03-11
FR2935536A1 (fr) 2010-03-05
CN102017092A (zh) 2011-04-13
JP5319764B2 (ja) 2013-10-16
US8679944B2 (en) 2014-03-25
KR101160316B1 (ko) 2012-06-26
TWI443730B (zh) 2014-07-01
KR20100130619A (ko) 2010-12-13
EP2324491B1 (fr) 2013-06-05
TW201027609A (en) 2010-07-16
CN102017092B (zh) 2012-10-03
EP2324491A1 (fr) 2011-05-25

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