FR3084520B1 - Procede de protection d'un circuit integre, et dispositif correspondant - Google Patents

Procede de protection d'un circuit integre, et dispositif correspondant Download PDF

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Publication number
FR3084520B1
FR3084520B1 FR1856886A FR1856886A FR3084520B1 FR 3084520 B1 FR3084520 B1 FR 3084520B1 FR 1856886 A FR1856886 A FR 1856886A FR 1856886 A FR1856886 A FR 1856886A FR 3084520 B1 FR3084520 B1 FR 3084520B1
Authority
FR
France
Prior art keywords
integrated circuit
protection method
corresponding device
charges
different
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1856886A
Other languages
English (en)
Other versions
FR3084520A1 (fr
Inventor
Pascal Fornara
Fabrice Marinet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1856886A priority Critical patent/FR3084520B1/fr
Priority to US16/518,755 priority patent/US10886240B2/en
Publication of FR3084520A1 publication Critical patent/FR3084520A1/fr
Application granted granted Critical
Publication of FR3084520B1 publication Critical patent/FR3084520B1/fr
Priority to US17/113,645 priority patent/US11329011B2/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/40—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering
    • H10W42/405—Arrangements for protection of devices protecting against tampering, e.g. unauthorised inspection or reverse engineering using active circuits
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D1/00—Resistors, capacitors or inductors
    • H10D1/40—Resistors
    • H10D1/43—Resistors having PN junctions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices

Landscapes

  • Semiconductor Integrated Circuits (AREA)
  • Protection Of Static Devices (AREA)
  • Emergency Protection Circuit Devices (AREA)

Abstract

Circuit intégré (CI) comprenant des moyens de protection dudit circuit intégré (CI) comportant un corps électriquement conducteur à potentiel flottant (PC) situé dans le circuit intégré (CI) et ayant une quantité initiale de charges électriques, des moyens de détection (MD) configurés pour détecter une quantité de charges électriques (AC) sur ledit corps (PC) différente de la quantité initiale de charges, et des moyens de commande (MCMD) configurés pour déclencher une action de protection si la quantité de charges détectée (AC) est différente de la quantité initiale.
FR1856886A 2018-07-25 2018-07-25 Procede de protection d'un circuit integre, et dispositif correspondant Active FR3084520B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1856886A FR3084520B1 (fr) 2018-07-25 2018-07-25 Procede de protection d'un circuit integre, et dispositif correspondant
US16/518,755 US10886240B2 (en) 2018-07-25 2019-07-22 Method for protecting an integrated circuit, and corresponding device
US17/113,645 US11329011B2 (en) 2018-07-25 2020-12-07 Method for protecting an integrated circuit, and corresponding device

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1856886A FR3084520B1 (fr) 2018-07-25 2018-07-25 Procede de protection d'un circuit integre, et dispositif correspondant
FR1856886 2018-07-25

Publications (2)

Publication Number Publication Date
FR3084520A1 FR3084520A1 (fr) 2020-01-31
FR3084520B1 true FR3084520B1 (fr) 2020-08-14

Family

ID=65685435

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1856886A Active FR3084520B1 (fr) 2018-07-25 2018-07-25 Procede de protection d'un circuit integre, et dispositif correspondant

Country Status (2)

Country Link
US (2) US10886240B2 (fr)
FR (1) FR3084520B1 (fr)

Family Cites Families (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6856581B1 (en) 2000-10-31 2005-02-15 International Business Machines Corporation Batteryless, oscillatorless, binary time cell usable as an horological device with associated programming methods and devices
US6541792B1 (en) 2001-09-14 2003-04-01 Hewlett-Packard Development Company, Llp Memory device having dual tunnel junction memory cells
FR2844090A1 (fr) 2002-08-27 2004-03-05 St Microelectronics Sa Cellule memoire pour registre non volatile a lecture rapide
EP1400887A1 (fr) 2002-09-20 2004-03-24 EM Microelectronic-Marin SA Dispositif de protection pour puce électronique comportant des informations confidentielles
JP2006513481A (ja) 2003-01-10 2006-04-20 コーニンクレッカ　フィリップス　エレクトロニクス　エヌ　ヴィ 不正操作から電子構成部品を保護する回路構成および方法
JP4462903B2 (ja) * 2003-11-18 2010-05-12 パナソニック株式会社 半導体ウェハ
US7202782B2 (en) * 2004-08-04 2007-04-10 Agere Systems Inc. Method and apparatus for disabling an integrated circuit (IC) when an attempt is made to bypass security on the IC
US8304313B2 (en) 2004-08-23 2012-11-06 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device and its manufacturing method
US8022460B2 (en) 2006-03-31 2011-09-20 Semiconductor Energy Laboratory Co., Ltd. Nonvolatile semiconductor memory device
FR2938953B1 (fr) 2008-11-21 2011-03-11 Innova Card Dispositif de protection d'un boitier de circuit integre electronique contre les intrusions par voie physique ou chimique.
US9442129B2 (en) * 2011-01-31 2016-09-13 Hitachi High-Technologies Corporation Automatic analyzer
FR2978867B1 (fr) 2011-08-01 2014-03-21 St Microelectronics Rousset Resistance ajustable
US8378710B1 (en) * 2011-09-20 2013-02-19 Nxp B.V. Secure device anti-tampering circuit
JP2013114729A (ja) 2011-11-30 2013-06-10 Toshiba Corp 不揮発性プログラマブルスイッチ
FR2985059B1 (fr) 2011-12-21 2014-01-10 Oberthur Technologies Dispositif de securisation d'un document electronique
DE102012200168A1 (de) * 2012-01-06 2013-07-11 Technische Universität Berlin Ladungsmesseinrichtung
FR2986356B1 (fr) 2012-01-27 2014-02-28 St Microelectronics Rousset Dispositif de protection d'un circuit integre contre des attaques en face arriere
FR2991083A1 (fr) 2012-05-24 2013-11-29 St Microelectronics Grenoble 2 Procede et dispositif de protection d'un circuit integre contre des attaques par sa face arriere
EP2680184A1 (fr) 2012-06-27 2014-01-01 EM Microelectronic-Marin SA Circuit intégré protégé contre des intrusions d'un pirate
JP2014022507A (ja) 2012-07-17 2014-02-03 Toshiba Corp 不揮発プログラマブルスイッチ
WO2015105687A1 (fr) 2014-01-08 2015-07-16 Stc.Unm Systèmes et procédés destinés à la génération de fonctions physiquement non clonables à partir de cellules de mémoire non volatile
US9965652B2 (en) 2014-08-06 2018-05-08 Maxim Integrated Products, Inc. Detecting and thwarting backside attacks on secured systems
FR3084492A1 (fr) 2018-07-30 2020-01-31 Stmicroelectronics (Rousset) Sas Procede de detection d'une attaque par un faisceau de particules electriquement chargees sur un circuit integre, et circuit integre correspondant

Also Published As

Publication number Publication date
FR3084520A1 (fr) 2020-01-31
US20200035623A1 (en) 2020-01-30
US11329011B2 (en) 2022-05-10
US10886240B2 (en) 2021-01-05
US20210091015A1 (en) 2021-03-25

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