FR3096830B1 - Elément d'interconnexion et son procédé de fabrication - Google Patents

Elément d'interconnexion et son procédé de fabrication Download PDF

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Publication number
FR3096830B1
FR3096830B1 FR1905576A FR1905576A FR3096830B1 FR 3096830 B1 FR3096830 B1 FR 3096830B1 FR 1905576 A FR1905576 A FR 1905576A FR 1905576 A FR1905576 A FR 1905576A FR 3096830 B1 FR3096830 B1 FR 3096830B1
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France
Prior art keywords
layer
interconnection element
cavity
copper
manufacturing process
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FR1905576A
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English (en)
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FR3096830A1 (fr
Inventor
Magali Gregoire
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STMicroelectronics Crolles 2 SAS
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STMicroelectronics Crolles 2 SAS
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Publication date
Application filed by STMicroelectronics Crolles 2 SAS filed Critical STMicroelectronics Crolles 2 SAS
Priority to FR1905576A priority Critical patent/FR3096830B1/fr
Priority to US16/881,689 priority patent/US11152259B2/en
Publication of FR3096830A1 publication Critical patent/FR3096830A1/fr
Application granted granted Critical
Publication of FR3096830B1 publication Critical patent/FR3096830B1/fr
Priority to US17/488,714 priority patent/US11610813B2/en
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Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/076—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers in via holes or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/694—Inorganic materials composed of nitrides
    • H10P14/6943—Inorganic materials composed of nitrides containing silicon
    • H10P14/69433—Inorganic materials composed of nitrides containing silicon the material being a silicon nitride not containing oxygen, e.g. SixNy or SixByNz
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/20—Dry etching; Plasma etching; Reactive-ion etching
    • H10P50/28—Dry etching; Plasma etching; Reactive-ion etching of insulating materials
    • H10P50/282—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials
    • H10P50/283—Dry etching; Plasma etching; Reactive-ion etching of insulating materials of inorganic materials by chemical means
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/035—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics combinations of barrier, adhesion or liner layers, e.g. multi-layered barrier layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/033—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics
    • H10W20/037—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers in openings in dielectrics the barrier, adhesion or liner layers being on top of a main fill metal
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/032—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers
    • H10W20/047—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein
    • H10W20/049—Manufacture or treatment of conductive parts of the interconnections of conductive barrier, adhesion or liner layers by introducing additional elements therein by diffusing alloying elements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/031—Manufacture or treatment of conductive parts of the interconnections
    • H10W20/056—Manufacture or treatment of conductive parts of the interconnections by filling conductive material into holes, grooves or trenches
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H10W20/077—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers on sidewalls or on top surfaces of conductors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/42—Vias, e.g. via plugs
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/425—Barrier, adhesion or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/41—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their conductive parts
    • H10W20/43—Layouts of interconnections

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Physics & Mathematics (AREA)
  • Geometry (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • General Chemical & Material Sciences (AREA)

Abstract

Elément d'interconnexion et son procédé de fabrication La présente description concerne un procédé de fabrication d'un élément d'interconnexion d'une structure d'interconnexion d'un circuit intégré, le procédé comprenant les étapes suivantes : a) graver une cavité (200) dans une première couche (202) isolante ; b) déposer une deuxième couche (204) en nitrure de silicium sur les parois et le fond de la cavité (200), la concentration en atomes d'azote dans la deuxième couche augmentant en s'éloignant d'une surface exposée (2041) de la deuxième couche (204) ; c) déposer une troisième couche (206) en cuivre sur la deuxième couche (204) ; d) chauffer pour former une quatrième couche (208) de siliciure de cuivre à partir des deuxième et troisième couches (204, 206) ; et e) remplir la cavité de cuivre (210). Figure pour l'abrégé : Fig. 2
FR1905576A 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication Active FR3096830B1 (fr)

Priority Applications (3)

Application Number Priority Date Filing Date Title
FR1905576A FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication
US16/881,689 US11152259B2 (en) 2019-05-27 2020-05-22 Interconnection element and method of manufacturing the same
US17/488,714 US11610813B2 (en) 2019-05-27 2021-09-29 Interconnection element and method of manufacturing the same

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1905576 2019-05-27
FR1905576A FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication

Publications (2)

Publication Number Publication Date
FR3096830A1 FR3096830A1 (fr) 2020-12-04
FR3096830B1 true FR3096830B1 (fr) 2021-06-18

Family

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Family Applications (1)

Application Number Title Priority Date Filing Date
FR1905576A Active FR3096830B1 (fr) 2019-05-27 2019-05-27 Elément d'interconnexion et son procédé de fabrication

Country Status (2)

Country Link
US (2) US11152259B2 (fr)
FR (1) FR3096830B1 (fr)

Family Cites Families (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
EP0535864B1 (fr) 1991-09-30 1998-07-29 AT&T Corp. Fabrication d'une région conductrice dans des dispositifs électroniques
US5391517A (en) 1993-09-13 1995-02-21 Motorola Inc. Process for forming copper interconnect structure
US6303505B1 (en) 1998-07-09 2001-10-16 Advanced Micro Devices, Inc. Copper interconnect with improved electromigration resistance
US6251775B1 (en) 1999-04-23 2001-06-26 International Business Machines Corporation Self-aligned copper silicide formation for improved adhesion/electromigration
US6046108A (en) 1999-06-25 2000-04-04 Taiwan Semiconductor Manufacturing Company Method for selective growth of Cu3 Ge or Cu5 Si for passivation of damascene copper structures and device manufactured thereby
SG125881A1 (en) 1999-12-03 2006-10-30 Lytle Steven Alan Define via in dual damascene process
JP4535629B2 (ja) * 2001-02-21 2010-09-01 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US6693356B2 (en) * 2002-03-27 2004-02-17 Texas Instruments Incorporated Copper transition layer for improving copper interconnection reliability
JP2003332426A (ja) * 2002-05-17 2003-11-21 Renesas Technology Corp 半導体装置の製造方法および半導体装置
WO2007100125A1 (fr) * 2006-02-28 2007-09-07 Advanced Interconnect Materials, Llc Dispositif semiconducteur, son procede de fabrication et materiau cible de pulverisation a utiliser dans ledit procede
JP4741965B2 (ja) * 2006-03-23 2011-08-10 ルネサスエレクトロニクス株式会社 半導体装置およびその製造方法
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
KR20130092884A (ko) * 2012-02-13 2013-08-21 에스케이하이닉스 주식회사 반도체 소자의 배선 구조체 및 제조 방법
US8981564B2 (en) * 2013-05-20 2015-03-17 Invensas Corporation Metal PVD-free conducting structures
US9673091B2 (en) * 2015-06-25 2017-06-06 Globalfoundries Inc. Structure for BEOL metal levels with multiple dielectric layers for improved dielectric to metal adhesion

Also Published As

Publication number Publication date
US20220020640A1 (en) 2022-01-20
FR3096830A1 (fr) 2020-12-04
US11152259B2 (en) 2021-10-19
US20200381297A1 (en) 2020-12-03
US11610813B2 (en) 2023-03-21

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