IL110181A - התקן מיקרופרוססור ואביזרים היקפיים - Google Patents

התקן מיקרופרוססור ואביזרים היקפיים

Info

Publication number
IL110181A
IL110181A IL110181A IL11018194A IL110181A IL 110181 A IL110181 A IL 110181A IL 110181 A IL110181 A IL 110181A IL 11018194 A IL11018194 A IL 11018194A IL 110181 A IL110181 A IL 110181A
Authority
IL
Israel
Prior art keywords
memory
signal
access
execution unit
clock cycles
Prior art date
Application number
IL110181A
Other languages
English (en)
Other versions
IL110181A0 (en
Inventor
Michael Cohen
Original Assignee
Softchip Israel Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Softchip Israel Ltd filed Critical Softchip Israel Ltd
Priority to IL110181A priority Critical patent/IL110181A/he
Publication of IL110181A0 publication Critical patent/IL110181A0/xx
Priority to EP95304221A priority patent/EP0690370A3/en
Priority to JP7186507A priority patent/JPH08328848A/ja
Priority to US08/496,351 priority patent/US5729766A/en
Publication of IL110181A publication Critical patent/IL110181A/he

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/16—Handling requests for interconnection or transfer for access to memory bus
    • G06F13/1668—Details of memory controller
    • G06F13/1689—Synchronisation and timing concerns
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/3005—Arrangements for executing specific machine instructions to perform operations for flow control
    • G06F9/30058—Conditional branch instructions
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30003—Arrangements for executing specific machine instructions
    • G06F9/30072—Arrangements for executing specific machine instructions to perform conditional operations, e.g. using predicates or guards
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/30145—Instruction analysis, e.g. decoding, instruction word fields
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/3017—Runtime instruction translation, e.g. macros
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3836—Instruction issuing, e.g. dynamic instruction scheduling or out of order instruction execution
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F9/00—Arrangements for program control, e.g. control units
    • G06F9/06—Arrangements for program control, e.g. control units using stored programs, i.e. using an internal store of processing equipment to receive or retain programs
    • G06F9/30—Arrangements for executing machine instructions, e.g. instruction decode
    • G06F9/38—Concurrent instruction execution, e.g. pipeline or look ahead
    • G06F9/3867—Concurrent instruction execution, e.g. pipeline or look ahead using instruction pipelines
    • G06F9/3869—Implementation aspects, e.g. pipeline latches; pipeline synchronisation and clocking
    • G—PHYSICS
    • G06—COMPUTING OR CALCULATING; COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2207/00—Indexing scheme relating to methods or arrangements for processing data by operating upon the order or content of the data handled
    • G06F2207/72—Indexing scheme relating to groups G06F7/72 - G06F7/729
    • G06F2207/7219—Countermeasures against side channel or fault attacks

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Software Systems (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Executing Machine-Instructions (AREA)
  • Microcomputers (AREA)
  • Memory System (AREA)
IL110181A 1994-06-30 1994-06-30 התקן מיקרופרוססור ואביזרים היקפיים IL110181A (he)

Priority Applications (4)

Application Number Priority Date Filing Date Title
IL110181A IL110181A (he) 1994-06-30 1994-06-30 התקן מיקרופרוססור ואביזרים היקפיים
EP95304221A EP0690370A3 (en) 1994-06-30 1995-06-19 Microprocessor device and peripheral devices
JP7186507A JPH08328848A (ja) 1994-06-30 1995-06-30 マイクロプロセッサ
US08/496,351 US5729766A (en) 1994-06-30 1995-06-30 System for memory unit receiving pseudo-random delay signal operative to access memory after delay and additional delay signal extending from termination of memory access

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
IL110181A IL110181A (he) 1994-06-30 1994-06-30 התקן מיקרופרוססור ואביזרים היקפיים

Publications (2)

Publication Number Publication Date
IL110181A0 IL110181A0 (en) 1994-10-07
IL110181A true IL110181A (he) 1998-02-08

Family

ID=11066292

Family Applications (1)

Application Number Title Priority Date Filing Date
IL110181A IL110181A (he) 1994-06-30 1994-06-30 התקן מיקרופרוססור ואביזרים היקפיים

Country Status (4)

Country Link
US (1) US5729766A (he)
EP (1) EP0690370A3 (he)
JP (1) JPH08328848A (he)
IL (1) IL110181A (he)

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KR100212142B1 (ko) * 1996-09-12 1999-08-02 윤종용 매크로 명령기능을 가진 동기식 반도체 메모리장치와 매크로 명령의 저장 및 실행방법
JPH1139868A (ja) * 1997-07-18 1999-02-12 Matsushita Electric Ind Co Ltd 半導体集積回路システム、半導体集積回路、及び半導体集積回路システムの駆動方法
US7587044B2 (en) * 1998-01-02 2009-09-08 Cryptography Research, Inc. Differential power analysis method and apparatus
US6338137B1 (en) * 1998-05-29 2002-01-08 Texas Instruments Incorporated Data processor having memory access unit with predetermined number of instruction cycles between activation and initial data transfer
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US6954873B2 (en) 2001-11-06 2005-10-11 Infineon Technologies Aktiengesellschaft Implementation of wait-states
JP3813930B2 (ja) * 2002-01-09 2006-08-23 松下電器産業株式会社 プロセッサ及びプログラム実行方法
DE10254658A1 (de) * 2002-11-22 2004-06-03 Philips Intellectual Property & Standards Gmbh Mikrocontroller und zugeordnetes Verfahren zum Abarbeiten der Programmierung des Mikrocontrollers
JP4511461B2 (ja) * 2002-12-12 2010-07-28 エイアールエム リミテッド データ処理システムでの処理動作マスキング
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JP4750350B2 (ja) 2003-03-13 2011-08-17 パナソニック株式会社 タスク切換装置、方法及びプログラム
WO2006116046A2 (en) * 2005-04-22 2006-11-02 Altrix Logic, Inc. Asynchronous processor
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US9627038B2 (en) 2013-03-15 2017-04-18 Intel Corporation Multiport memory cell having improved density area
US9582322B2 (en) 2013-03-15 2017-02-28 Soft Machines Inc. Method and apparatus to avoid deadlock during instruction scheduling using dynamic port remapping
US20140281116A1 (en) 2013-03-15 2014-09-18 Soft Machines, Inc. Method and Apparatus to Speed up the Load Access and Data Return Speed Path Using Early Lower Address Bits
US9436476B2 (en) 2013-03-15 2016-09-06 Soft Machines Inc. Method and apparatus for sorting elements in hardware structures
WO2015175555A1 (en) 2014-05-12 2015-11-19 Soft Machines, Inc. Method and apparatus for providing hardware support for self-modifying code
US9378363B1 (en) * 2014-10-08 2016-06-28 Amazon Technologies, Inc. Noise injected virtual timer
US9495111B2 (en) 2014-10-10 2016-11-15 The Boeing Company System and method for reducing information leakage from memory
US10217498B2 (en) 2016-09-12 2019-02-26 Qualcomm Incorporated Techniques for preventing tampering with PROM settings
US10082975B1 (en) 2017-03-02 2018-09-25 Micron Technology, Inc. Obfuscation-enhanced memory encryption

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Also Published As

Publication number Publication date
US5729766A (en) 1998-03-17
JPH08328848A (ja) 1996-12-13
EP0690370A2 (en) 1996-01-03
EP0690370A3 (en) 1997-04-23
IL110181A0 (en) 1994-10-07

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