IT1255960B - Struttura periferica di una piastrina come un dispositivo a semiconduttore e suo procedimento di fabbricazione - Google Patents

Struttura periferica di una piastrina come un dispositivo a semiconduttore e suo procedimento di fabbricazione

Info

Publication number
IT1255960B
IT1255960B ITMI922707A ITMI922707A IT1255960B IT 1255960 B IT1255960 B IT 1255960B IT MI922707 A ITMI922707 A IT MI922707A IT MI922707 A ITMI922707 A IT MI922707A IT 1255960 B IT1255960 B IT 1255960B
Authority
IT
Italy
Prior art keywords
insulating layer
semiconductor device
plate
manufacturing procedure
peripheral structure
Prior art date
Application number
ITMI922707A
Other languages
English (en)
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of ITMI922707A0 publication Critical patent/ITMI922707A0/it
Publication of ITMI922707A1 publication Critical patent/ITMI922707A1/it
Application granted granted Critical
Publication of IT1255960B publication Critical patent/IT1255960B/it

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P54/00—Cutting or separating of wafers, substrates or parts of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/021—Manufacture or treatment of interconnections within wafers or substrates
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W42/00—Arrangements for protection of devices
    • H10W42/121—Arrangements for protection of devices protecting against mechanical damage
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/301—Marks applied to devices, e.g. for alignment or identification for alignment
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W46/00—Marks applied to devices, e.g. for alignment or identification
    • H10W46/501—Marks applied to devices, e.g. for alignment or identification for use before dicing
    • H10W46/503—Located in scribe lines

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Dicing (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)

Abstract

Su una superficie di un substrato (2) di semiconduttore entro una regione (60, 160) di una regione di formazione di dispositivi, è formato un transistor MOS (30) includente un elettrodo di porte (4), pellicola (5) di ossido di porta e percorso sorgente-pozzo (6). Uno strato isolante (7, 107) è formato sulla superficie del substrato di semiconduttore (2). In una apertura (52) dello strato isolante (7, 107) al di sopra della sorgente-pozzo (6), è formato un elemento a tappo o cilindretto di tungsteno (1b, 10b). In corrispondenza di una porzione (50) a linea di scubettatura, lo strato isolante (7, 107) presenta una porzione a solco (51). La porzione a solco (51) è formata per circondare la regione formante i dispositivi. Un percorso di tungsteno (1a, 10a) avente una superficie di sommità a proseguimento della superficie di sommità dello strato isolante (7, 107) è formato nel solco (51). Tramite tale dispositivo a semiconduttore, corto-circuitazione tra piazzuole di collegamento e simili può essere impedita, e l'affidabilità può essere migliorata.
ITMI922707A 1991-11-27 1992-11-26 Struttura periferica di una piastrina come un dispositivo a semiconduttore e suo procedimento di fabbricazione IT1255960B (it)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP3312257A JP2890380B2 (ja) 1991-11-27 1991-11-27 半導体装置およびその製造方法

Publications (3)

Publication Number Publication Date
ITMI922707A0 ITMI922707A0 (it) 1992-11-26
ITMI922707A1 ITMI922707A1 (it) 1994-05-26
IT1255960B true IT1255960B (it) 1995-11-17

Family

ID=18027064

Family Applications (1)

Application Number Title Priority Date Filing Date
ITMI922707A IT1255960B (it) 1991-11-27 1992-11-26 Struttura periferica di una piastrina come un dispositivo a semiconduttore e suo procedimento di fabbricazione

Country Status (6)

Country Link
US (2) US5945716A (it)
JP (1) JP2890380B2 (it)
KR (1) KR960016772B1 (it)
DE (1) DE4239457C2 (it)
IT (1) IT1255960B (it)
TW (1) TW222711B (it)

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH07176688A (ja) * 1993-12-20 1995-07-14 Mitsubishi Electric Corp 半導体集積回路
US6184118B1 (en) * 1998-03-02 2001-02-06 United Microelectronics Corp. Method for preventing the peeling of the tungsten metal after the metal-etching process
JPH11340167A (ja) 1998-05-22 1999-12-10 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2000269293A (ja) * 1999-03-18 2000-09-29 Fujitsu Ltd 半導体装置
JP3548061B2 (ja) * 1999-10-13 2004-07-28 三洋電機株式会社 半導体装置の製造方法
US6610592B1 (en) * 2000-04-24 2003-08-26 Taiwan Semiconductor Manufacturing Company Method for integrating low-K materials in semiconductor fabrication
US6630746B1 (en) * 2000-05-09 2003-10-07 Motorola, Inc. Semiconductor device and method of making the same
JP2003197854A (ja) * 2001-12-26 2003-07-11 Nec Electronics Corp 両面接続型半導体装置、多段積層型半導体装置、その製造方法および該半導体装置を搭載した電子部品
JP4434606B2 (ja) 2003-03-27 2010-03-17 株式会社東芝 半導体装置、半導体装置の製造方法
JP2005109145A (ja) 2003-09-30 2005-04-21 Toshiba Corp 半導体装置
FR2893182B1 (fr) * 2005-11-10 2007-12-28 Atmel Grenoble Soc Par Actions Procede de decoupe de puces de circuit-integre sur substrat aminci
ITTO20100332A1 (it) * 2010-04-21 2011-10-22 St Microelectronics Srl Procedimento per la fabbricazione di piastrine semiconduttrici e piastrina semiconduttrice con trincea di protezione
JP2017028056A (ja) * 2015-07-21 2017-02-02 トヨタ自動車株式会社 半導体装置の製造方法
US10109599B2 (en) * 2016-12-21 2018-10-23 Globalfoundries Inc. Integrated circuit structure with continuous metal crack stop
KR102542621B1 (ko) * 2018-08-17 2023-06-15 삼성전자주식회사 반도체 장치
JP7443097B2 (ja) * 2020-03-09 2024-03-05 キオクシア株式会社 半導体ウェハおよび半導体チップ
KR20240009279A (ko) * 2022-07-13 2024-01-22 에스케이하이닉스 주식회사 기판 분단을 포함한 반도체 칩 제조 방법

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4392150A (en) * 1980-10-27 1983-07-05 National Semiconductor Corporation MOS Integrated circuit having refractory metal or metal silicide interconnect layer
JPS5776860A (en) * 1980-10-31 1982-05-14 Toshiba Corp Semiconductor device and its manufacture
US5045916A (en) * 1985-01-22 1991-09-03 Fairchild Semiconductor Corporation Extended silicide and external contact technology
US4745081A (en) * 1985-10-31 1988-05-17 International Business Machines Corporation Method of trench filling
JPS63127551A (ja) * 1986-11-17 1988-05-31 Toshiba Corp 半導体装置の製造方法
US4977439A (en) * 1987-04-03 1990-12-11 Esquivel Agerico L Buried multilevel interconnect system
US4879257A (en) * 1987-11-18 1989-11-07 Lsi Logic Corporation Planarization process
JPH01186655A (ja) * 1988-01-14 1989-07-26 Fujitsu Ltd 半導体集積回路
JP2769331B2 (ja) * 1988-09-12 1998-06-25 株式会社日立製作所 半導体集積回路の製造方法
JPH02188942A (ja) * 1989-01-17 1990-07-25 Fujitsu Ltd 多層配線構造を備えた半導体装置の製造方法
JP2737979B2 (ja) * 1989-02-10 1998-04-08 三菱電機株式会社 半導体装置
JPH0750700B2 (ja) * 1989-06-27 1995-05-31 三菱電機株式会社 半導体チップの製造方法
US4987099A (en) * 1989-12-29 1991-01-22 North American Philips Corp. Method for selectively filling contacts or vias or various depths with CVD tungsten

Also Published As

Publication number Publication date
ITMI922707A0 (it) 1992-11-26
JPH05152433A (ja) 1993-06-18
US5945716A (en) 1999-08-31
DE4239457A1 (en) 1993-06-03
KR960016772B1 (ko) 1996-12-20
ITMI922707A1 (it) 1994-05-26
TW222711B (it) 1994-04-21
DE4239457C2 (de) 1995-04-06
US6211070B1 (en) 2001-04-03
KR930011167A (ko) 1993-06-23
JP2890380B2 (ja) 1999-05-10

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Legal Events

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0001 Granted
TA Fee payment date (situation as of event date), data collected since 19931001

Effective date: 19971129