IT1295873B1 - Processo per la fabbricazione di dispositivo a gate mos con celle autoallineate - Google Patents
Processo per la fabbricazione di dispositivo a gate mos con celle autoallineateInfo
- Publication number
- IT1295873B1 IT1295873B1 IT97MI002399A ITMI972399A IT1295873B1 IT 1295873 B1 IT1295873 B1 IT 1295873B1 IT 97MI002399 A IT97MI002399 A IT 97MI002399A IT MI972399 A ITMI972399 A IT MI972399A IT 1295873 B1 IT1295873 B1 IT 1295873B1
- Authority
- IT
- Italy
- Prior art keywords
- self
- manufacturing
- mos device
- gate mos
- aligned cells
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
- H10D84/101—Integrated devices comprising main components and built-in components, e.g. IGBT having built-in freewheel diode
- H10D84/141—VDMOS having built-in components
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D12/00—Bipolar devices controlled by the field effect, e.g. insulated-gate bipolar transistors [IGBT]
- H10D12/411—Insulated-gate bipolar transistors [IGBT]
- H10D12/441—Vertical IGBTs
- H10D12/461—Vertical IGBTs having non-planar surfaces, e.g. having trenches, recesses or pillars in the surfaces of the emitter, base or collector regions
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
- H10D18/01—Manufacture or treatment
- H10D18/031—Manufacture or treatment of lateral or planar thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D18/00—Thyristors
- H10D18/251—Lateral thyristors
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D30/00—Field-effect transistors [FET]
- H10D30/60—Insulated-gate field-effect transistors [IGFET]
- H10D30/64—Double-diffused metal-oxide semiconductor [DMOS] FETs
- H10D30/66—Vertical DMOS [VDMOS] FETs
- H10D30/665—Vertical DMOS [VDMOS] FETs having edge termination structures
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/111—Field plates
- H10D64/112—Field plates comprising multiple field plate segments
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/252—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices
- H10D64/2527—Source or drain electrodes for field-effect devices for vertical or pseudo-vertical devices for vertical devices wherein the source or drain electrodes are recessed in semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/23—Electrodes carrying the current to be rectified, amplified, oscillated or switched, e.g. sources, drains, anodes or cathodes
- H10D64/251—Source or drain electrodes for field-effect devices
- H10D64/256—Source or drain electrodes for field-effect devices for lateral devices wherein the source or drain electrodes are recessed in semiconductor bodies
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
- H10D64/00—Electrodes of devices having potential barriers
- H10D64/20—Electrodes characterised by their shapes, relative sizes or dispositions
- H10D64/27—Electrodes not carrying the current to be rectified, amplified, oscillated or switched, e.g. gates
- H10D64/311—Gate electrodes for field-effect devices
- H10D64/411—Gate electrodes for field-effect devices for FETs
- H10D64/511—Gate electrodes for field-effect devices for FETs for IGFETs
- H10D64/517—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers
- H10D64/519—Gate electrodes for field-effect devices for FETs for IGFETs characterised by the conducting layers characterised by their top-view geometrical layouts
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US2949196P | 1996-10-25 | 1996-10-25 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| ITMI972399A1 ITMI972399A1 (it) | 1999-04-24 |
| IT1295873B1 true IT1295873B1 (it) | 1999-05-28 |
Family
ID=21849286
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| IT97MI002399A IT1295873B1 (it) | 1996-10-25 | 1997-10-24 | Processo per la fabbricazione di dispositivo a gate mos con celle autoallineate |
Country Status (10)
| Country | Link |
|---|---|
| US (2) | US6043126A (it) |
| JP (1) | JP3117426B2 (it) |
| KR (1) | KR100270796B1 (it) |
| CN (1) | CN1104043C (it) |
| DE (1) | DE19747159B4 (it) |
| FR (1) | FR2756102A1 (it) |
| GB (1) | GB2318685B (it) |
| IT (1) | IT1295873B1 (it) |
| SG (1) | SG67999A1 (it) |
| TW (1) | TW391037B (it) |
Families Citing this family (37)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE69523576D1 (de) * | 1995-06-16 | 2001-12-06 | St Microelectronics Srl | Verfahren zur Herstellung einer Halbleiteranordnung mit selbstjustiertem Polycid |
| JP2000260953A (ja) * | 1998-11-10 | 2000-09-22 | Texas Instr Inc <Ti> | ソースとドレイン端子用の拡大されたコンタクト領域を有するゲートデバイス及びその製造方法 |
| JP3317347B2 (ja) * | 1999-09-02 | 2002-08-26 | 日本電気株式会社 | ダイオードを備えた半導体装置およびその製造方法 |
| US6312993B1 (en) * | 2000-02-29 | 2001-11-06 | General Semiconductor, Inc. | High speed trench DMOS |
| US6482681B1 (en) | 2000-05-05 | 2002-11-19 | International Rectifier Corporation | Hydrogen implant for buffer zone of punch-through non epi IGBT |
| US6242288B1 (en) * | 2000-05-05 | 2001-06-05 | International Rectifier Corp. | Anneal-free process for forming weak collector |
| EP1158583A1 (en) * | 2000-05-23 | 2001-11-28 | STMicroelectronics S.r.l. | Low on-resistance LDMOS |
| US6784486B2 (en) * | 2000-06-23 | 2004-08-31 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions therein |
| US6781194B2 (en) * | 2001-04-11 | 2004-08-24 | Silicon Semiconductor Corporation | Vertical power devices having retrograded-doped transition regions and insulated trench-based electrodes therein |
| EP1247346A1 (en) | 2000-12-20 | 2002-10-09 | Koninklijke Philips Electronics N.V. | Processing device for the contactless communication with a data carrier which is detachably connected to the processing device |
| JP4198469B2 (ja) * | 2001-04-11 | 2008-12-17 | シリコン・セミコンダクター・コーポレイション | パワーデバイスとその製造方法 |
| US6767797B2 (en) | 2002-02-01 | 2004-07-27 | Agere Systems Inc. | Method of fabricating complementary self-aligned bipolar transistors |
| DE10238590B4 (de) * | 2002-08-22 | 2007-02-15 | Infineon Technologies Ag | Verfahren zur Erzeugung einer Struktur auf einem Substrat |
| JP2004221234A (ja) * | 2003-01-14 | 2004-08-05 | Matsushita Electric Ind Co Ltd | 半導体装置及びその製造方法 |
| JP3906184B2 (ja) * | 2003-06-11 | 2007-04-18 | 株式会社東芝 | 半導体装置およびその製造方法 |
| US6987305B2 (en) * | 2003-08-04 | 2006-01-17 | International Rectifier Corporation | Integrated FET and schottky device |
| US6964911B2 (en) * | 2003-09-23 | 2005-11-15 | Freescale Semiconductor, Inc. | Method for forming a semiconductor device having isolation regions |
| KR100612072B1 (ko) * | 2004-04-27 | 2006-08-14 | 이태복 | 고 내압용 반도체 소자 및 그 제조방법 |
| KR100572359B1 (ko) | 2004-06-14 | 2006-04-18 | 노틸러스효성 주식회사 | 자동화 기기의 현송 주기 최적화 방법 |
| US7736984B2 (en) * | 2005-09-23 | 2010-06-15 | Semiconductor Components Industries, Llc | Method of forming a low resistance semiconductor contact and structure therefor |
| JP2008078396A (ja) * | 2006-09-21 | 2008-04-03 | Nec Electronics Corp | 半導体装置 |
| US7564099B2 (en) | 2007-03-12 | 2009-07-21 | International Rectifier Corporation | Monolithic MOSFET and Schottky diode device |
| US7646058B2 (en) * | 2007-06-05 | 2010-01-12 | Force-Mos Technology Corporation | Device configuration and method to manufacture trench MOSFET with solderable front metal |
| US8188538B2 (en) | 2008-12-25 | 2012-05-29 | Rohm Co., Ltd. | Semiconductor device and method of manufacturing semiconductor device |
| JP2010238738A (ja) | 2009-03-30 | 2010-10-21 | Toshiba Corp | 半導体装置および半導体装置の製造方法 |
| CN102087963B (zh) * | 2009-12-04 | 2013-08-14 | 无锡华润上华半导体有限公司 | 多晶硅层的蚀刻方法 |
| TWI425575B (zh) * | 2010-07-09 | 2014-02-01 | 陳自雄 | 低閘容金氧半p-n接面二極體結構及其製作方法 |
| TWI422041B (zh) | 2010-09-01 | 2014-01-01 | 節能元件股份有限公司 | 溝渠隔絕式金氧半p-n接面二極體結構及其製作方法 |
| US8735289B2 (en) * | 2010-11-29 | 2014-05-27 | Infineon Technologies Ag | Method of contacting a doping region in a semiconductor substrate |
| US8455948B2 (en) | 2011-01-07 | 2013-06-04 | Infineon Technologies Austria Ag | Transistor arrangement with a first transistor and with a plurality of second transistors |
| US8569842B2 (en) | 2011-01-07 | 2013-10-29 | Infineon Technologies Austria Ag | Semiconductor device arrangement with a first semiconductor device and with a plurality of second semiconductor devices |
| US8759939B2 (en) * | 2012-01-31 | 2014-06-24 | Infineon Technologies Dresden Gmbh | Semiconductor arrangement with active drift zone |
| CN103632962A (zh) * | 2012-08-20 | 2014-03-12 | 北大方正集团有限公司 | 一种dmos管的制造方法及装置 |
| US9230807B2 (en) * | 2012-12-18 | 2016-01-05 | General Electric Company | Systems and methods for ohmic contacts in silicon carbide devices |
| JP5602256B2 (ja) * | 2013-01-11 | 2014-10-08 | 株式会社東芝 | 半導体装置の製造方法 |
| US9400513B2 (en) | 2014-06-30 | 2016-07-26 | Infineon Technologies Austria Ag | Cascode circuit |
| JP6168370B2 (ja) * | 2015-12-17 | 2017-07-26 | ローム株式会社 | SiC電界効果トランジスタ |
Family Cites Families (23)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4757025A (en) * | 1985-03-25 | 1988-07-12 | Motorola Inc. | Method of making gate turn off switch with anode short and buried base |
| US4895810A (en) * | 1986-03-21 | 1990-01-23 | Advanced Power Technology, Inc. | Iopographic pattern delineated power mosfet with profile tailored recessed source |
| EP0272755B1 (en) * | 1986-12-23 | 1994-03-16 | Philips Electronics Uk Limited | A method of manufacturing a semiconductor device |
| JPH0834311B2 (ja) * | 1987-06-10 | 1996-03-29 | 日本電装株式会社 | 半導体装置の製造方法 |
| US5173435A (en) * | 1987-11-11 | 1992-12-22 | Mitsubishi Denki Kabushiki Kaisha | Insulated gate bipolar transistor |
| US5342797A (en) * | 1988-10-03 | 1994-08-30 | National Semiconductor Corporation | Method for forming a vertical power MOSFET having doped oxide side wall spacers |
| JPH02119184A (ja) * | 1988-10-28 | 1990-05-07 | Hitachi Ltd | 絶縁ゲート半導体装置およびその製造方法 |
| JPH02185069A (ja) * | 1988-12-02 | 1990-07-19 | Motorola Inc | 高エネルギー阻止能力及び温度補償された阻止電圧を具備する半導体デバイス |
| US5119162A (en) * | 1989-02-10 | 1992-06-02 | Texas Instruments Incorporated | Integrated power DMOS circuit with protection diode |
| US4960723A (en) * | 1989-03-30 | 1990-10-02 | Motorola, Inc. | Process for making a self aligned vertical field effect transistor having an improved source contact |
| US5234851A (en) * | 1989-09-05 | 1993-08-10 | General Electric Company | Small cell, low contact assistance rugged power field effect devices and method of fabrication |
| US5040045A (en) * | 1990-05-17 | 1991-08-13 | U.S. Philips Corporation | High voltage MOS transistor having shielded crossover path for a high voltage connection bus |
| US5404040A (en) * | 1990-12-21 | 1995-04-04 | Siliconix Incorporated | Structure and fabrication of power MOSFETs, including termination structures |
| US5155052A (en) * | 1991-06-14 | 1992-10-13 | Davies Robert B | Vertical field effect transistor with improved control of low resistivity region geometry |
| US5304837A (en) * | 1992-01-08 | 1994-04-19 | Siemens Aktiengesellschaft | Monolithically integrated temperature sensor for power semiconductor components |
| GB9219268D0 (en) * | 1992-09-11 | 1992-10-28 | Inmos Ltd | Semiconductor device incorporating a contact and manufacture thereof |
| JP2944840B2 (ja) * | 1993-03-12 | 1999-09-06 | 株式会社日立製作所 | 電力用半導体装置 |
| DE69325645T2 (de) * | 1993-04-21 | 1999-12-09 | Consorzio Per La Ricerca Sulla Microelettronica Nel Mezzogiorno, Catania | Integrierte Schutzschaltungsstruktur zum Schutz von logischen MOS-Leistungshalbleitenbauelementen von elektrostatischen Entladungen |
| EP0658940A1 (de) * | 1993-11-23 | 1995-06-21 | Siemens Aktiengesellschaft | Durch Feldeffekt steuerbares Halbleiterbauelement |
| KR0143459B1 (ko) * | 1995-05-22 | 1998-07-01 | 한민구 | 모오스 게이트형 전력 트랜지스터 |
| US5631484A (en) * | 1995-12-26 | 1997-05-20 | Motorola, Inc. | Method of manufacturing a semiconductor device and termination structure |
| US5677562A (en) * | 1996-05-14 | 1997-10-14 | General Instrument Corporation Of Delaware | Planar P-N junction semiconductor structure with multilayer passivation |
| US5825065A (en) * | 1997-01-14 | 1998-10-20 | Texas Instruments Incorporated | Low voltage DMOS transistor |
-
1997
- 1997-10-22 US US08/956,062 patent/US6043126A/en not_active Expired - Lifetime
- 1997-10-23 SG SG1997003850A patent/SG67999A1/en unknown
- 1997-10-24 TW TW086115750A patent/TW391037B/zh not_active IP Right Cessation
- 1997-10-24 JP JP09330763A patent/JP3117426B2/ja not_active Expired - Fee Related
- 1997-10-24 IT IT97MI002399A patent/IT1295873B1/it active IP Right Grant
- 1997-10-24 GB GB9722653A patent/GB2318685B/en not_active Expired - Fee Related
- 1997-10-24 DE DE19747159A patent/DE19747159B4/de not_active Expired - Fee Related
- 1997-10-24 FR FR9713341A patent/FR2756102A1/fr not_active Withdrawn
- 1997-10-25 CN CN97114151A patent/CN1104043C/zh not_active Expired - Fee Related
- 1997-10-25 KR KR1019970055065A patent/KR100270796B1/ko not_active Expired - Fee Related
-
1999
- 1999-11-03 US US09/432,210 patent/US6144065A/en not_active Expired - Lifetime
Also Published As
| Publication number | Publication date |
|---|---|
| GB2318685B (en) | 2002-01-02 |
| DE19747159B4 (de) | 2006-11-23 |
| JPH10189969A (ja) | 1998-07-21 |
| SG67999A1 (en) | 1999-10-19 |
| ITMI972399A1 (it) | 1999-04-24 |
| DE19747159A1 (de) | 1998-05-07 |
| JP3117426B2 (ja) | 2000-12-11 |
| TW391037B (en) | 2000-05-21 |
| KR100270796B1 (ko) | 2000-11-01 |
| GB9722653D0 (en) | 1997-12-24 |
| FR2756102A1 (fr) | 1998-05-22 |
| KR19980033182A (ko) | 1998-07-25 |
| GB2318685A (en) | 1998-04-29 |
| CN1104043C (zh) | 2003-03-26 |
| US6043126A (en) | 2000-03-28 |
| CN1184328A (zh) | 1998-06-10 |
| US6144065A (en) | 2000-11-07 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| 0001 | Granted |