JP2000208698A5 - - Google Patents

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Publication number
JP2000208698A5
JP2000208698A5 JP1999009763A JP976399A JP2000208698A5 JP 2000208698 A5 JP2000208698 A5 JP 2000208698A5 JP 1999009763 A JP1999009763 A JP 1999009763A JP 976399 A JP976399 A JP 976399A JP 2000208698 A5 JP2000208698 A5 JP 2000208698A5
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JP
Japan
Prior art keywords
wiring layer
semiconductor
base material
insulating base
interposer
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Pending
Application number
JP1999009763A
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JP2000208698A (ja
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Priority to JP11009763A priority Critical patent/JP2000208698A/ja
Priority claimed from JP11009763A external-priority patent/JP2000208698A/ja
Priority to KR1020000002003A priority patent/KR100615019B1/ko
Priority to US09/484,032 priority patent/US6239496B1/en
Publication of JP2000208698A publication Critical patent/JP2000208698A/ja
Priority to US09/828,131 priority patent/US6413798B2/en
Priority to KR10-2003-0020119A priority patent/KR100507300B1/ko
Publication of JP2000208698A5 publication Critical patent/JP2000208698A5/ja
Pending legal-status Critical Current

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【特許請求の範囲】
【請求項１】 配線層が形成されたインターポーザの厚さより薄い薄型シリコンチップを、該薄型シリコンチップより大きい穴を有した前記インターボ一ザの前記穴に配置して、前記薄型シリコンチップの電極と前記インターポーザの配線層とを電気的に接続した後封止した半導体パッケージが実装基板上に複数個積層された構造を有する半導体装置であって、前記半導体パッケージの所定の電極を、それぞれ上下段の半導体パッケージ間で導電対にて接続したことを特徴とする半導体装置。
【請求項２】 前記薄型シリコンチップの電極と前記インターポーザの配線層とは、ＴＡＢ接続法またはワイヤボンディング法によって接続したことを特徴とする請求項１記載の半導体装置。
【請求項３】 配線層が形成されたインターポーザの前記配線層と薄型シリコンチップの電極部とを異方性導電膜を用いて電気的及び機械的に接続し、前記インターポーザの前記配線層を前記薄型シリコンチップの外側へ導出した半導体パッケージが実装基板上に複数個積層された構造を有する半導体装置であって、前記半導体パッケージの所定の電極を、それぞれ上下段の半導体パッケージ間で導電体にて接続したことを特徴とする半導体装置。
【請求項４】 前記各半導体パッケージは、前記薄型シリコンチップ表面を表裏反対にして積層し、所定の電極をそれぞれ電気的に接続したことを特徴とする請求項１乃至請求項３記載の半導体装置。
【請求項５】 半導体パッケージにおいて、
（ａ）中央部にデバイスホールを有する絶縁性基材と、
（ｂ）前記絶縁性基材の表面に配設された配線層と、
（ｃ）その底面が前記絶縁性基材の底面の位置と一致すると共に、その上面が前記絶縁性基材と直接に接触しないように前記デバイスホール内に配設された、前記絶縁性基材よりも薄い半導体チップと、
（ｄ）前記半導体チップと前記配線層とを接続するためのインナーリード群と、
（ｅ）前記配線層に接続された接続用ランドと、を具備したことを特徴とする半導体パッケージ。
請求項５に係る発明の特徴は、半導体パッケージにおいて、（ａ）中央部にデバイスホールを有する絶縁性基材と、（ｂ）前記絶縁性基材の表面に配設された配線層と、（ｃ）その底面が前記絶縁性基材の底面の位置と一致すると共に、その上面が前記絶縁性基材と直接に接触しないように前記デバイスホール内に配設された、前記絶縁性基材よりも薄い半導体チップと、（ｄ）前記半導体チップと前記配線層とを接続するためのインナーリード群と、（ｅ）前記配線層に接続された接続用ランドと、を具備したことにある。
JP11009763A 1998-01-18 1999-01-18 半導体装置 Pending JP2000208698A (ja)

Priority Applications (5)

Application Number Priority Date Filing Date Title
JP11009763A JP2000208698A (ja) 1999-01-18 1999-01-18 半導体装置
KR1020000002003A KR100615019B1 (ko) 1999-01-18 2000-01-17 반도체 패키지, 멀티칩 모듈 및 그 제조방법
US09/484,032 US6239496B1 (en) 1999-01-18 2000-01-18 Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
US09/828,131 US6413798B2 (en) 1998-01-18 2001-04-09 Package having very thin semiconductor chip, multichip module assembled by the package, and method for manufacturing the same
KR10-2003-0020119A KR100507300B1 (ko) 1999-01-18 2003-03-31 멀티칩 모듈 및 그 제조방법

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11009763A JP2000208698A (ja) 1999-01-18 1999-01-18 半導体装置

Publications (2)

Publication Number Publication Date
JP2000208698A JP2000208698A (ja) 2000-07-28
JP2000208698A5 true JP2000208698A5 (ja) 2006-02-16

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JP11009763A Pending JP2000208698A (ja) 1998-01-18 1999-01-18 半導体装置

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US (2) US6239496B1 (ja)
JP (1) JP2000208698A (ja)
KR (2) KR100615019B1 (ja)

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