JPH01100457U - - Google Patents

Info

Publication number
JPH01100457U
JPH01100457U JP1987195253U JP19525387U JPH01100457U JP H01100457 U JPH01100457 U JP H01100457U JP 1987195253 U JP1987195253 U JP 1987195253U JP 19525387 U JP19525387 U JP 19525387U JP H01100457 U JPH01100457 U JP H01100457U
Authority
JP
Japan
Prior art keywords
outer frame
lead pattern
metal
insulating film
semiconductor chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987195253U
Other languages
English (en)
Other versions
JP2516390Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987195253U priority Critical patent/JP2516390Y2/ja
Publication of JPH01100457U publication Critical patent/JPH01100457U/ja
Application granted granted Critical
Publication of JP2516390Y2 publication Critical patent/JP2516390Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す平面図、第２図
は第１図の―断面図、第３図乃至第５図は従
来例を示す断面図及び平面図である。 １……リードフレーム、２……半導体チツプ、
３……インナーリード、４……外部リード、５…
…外枠、６……タイバー、７……金属箔、８……
絶縁フイルム、９……接続領域、１０……ワイヤ
ー。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードパターンを支持固定する金属製の外枠と
    、前記外枠に連結支持され前記外枠で囲まれた領
    域内の略中心部分を取り囲み、且つその先端部の
    長さが少なくとも交互に異なる様に延在された金
    属製リードパターンと、前記半導体チツプの大き
    さに対応してその大きさが任意に設定され、前記
    リードパターン上に接着された矩形状の絶縁フイ
    ルムと、前記フイルム上に貼着されボンデイング
    接続される接続領域を有する金属箔と、前記金属
    箔上に固着された前記半導体チツプと前記リード
    パターンの一端とを接続するボンデイングワイヤ
    ーとを具備したことを特徴とする半導体装置。
JP1987195253U 1987-12-23 1987-12-23 半導体装置 Expired - Lifetime JP2516390Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987195253U JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Publications (2)

Publication Number Publication Date
JPH01100457U true JPH01100457U (ja) 1989-07-05
JP2516390Y2 JP2516390Y2 (ja) 1996-11-06

Family

ID=31485939

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987195253U Expired - Lifetime JP2516390Y2 (ja) 1987-12-23 1987-12-23 半導体装置

Country Status (1)

Country Link
JP (1) JP2516390Y2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20010097511A (ko) * 2000-04-24 2001-11-08 이중구 이층형 칩 스케일 반도체 팩키지 및, 그것의 제조 방법

Also Published As

Publication number Publication date
JP2516390Y2 (ja) 1996-11-06

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