JPH0195760U - - Google Patents

Info

Publication number
JPH0195760U
JPH0195760U JP1987192376U JP19237687U JPH0195760U JP H0195760 U JPH0195760 U JP H0195760U JP 1987192376 U JP1987192376 U JP 1987192376U JP 19237687 U JP19237687 U JP 19237687U JP H0195760 U JPH0195760 U JP H0195760U
Authority
JP
Japan
Prior art keywords
tab
protrusion
outer frame
semiconductor chip
lead patterns
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987192376U
Other languages
English (en)
Other versions
JP2529366Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987192376U priority Critical patent/JP2529366Y2/ja
Publication of JPH0195760U publication Critical patent/JPH0195760U/ja
Application granted granted Critical
Publication of JP2529366Y2 publication Critical patent/JP2529366Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Die Bonding (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図は本考案の実施例を示す断面図、第２図
は第１図の―断面図、第３図乃至第５図は従
来例を示す断面図及び平面図である。 １……リードフレーム、２……半導体チツプ、
３……インナーリード、４……外部リード、５…
…外枠、６……タイバー、７……タブ、８……絶
縁フイルム、９……突出部、１０……ワイヤー。

Claims (1)

    【実用新案登録請求の範囲】
  1. リードパターンを支持固定する金属製の外枠と
    、前記外枠に連結支持されてこの外枠で囲まれた
    領域内に延在され、且つその先端が半導体チツプ
    を固着する突出部を有したタブを取り囲む様に配
    設された多数の金属製リードパターンと、前記タ
    ブの突出部を囲むと共に前記半導体チツプの大き
    さに対応してその大きさが任意に設定され前記リ
    ードパターン上に接着された矩形状の絶縁フイル
    ムと、前記タブの突出部と密接させ前記絶縁フイ
    ルム上に固着された半導体チツプとを具備したこ
    とを特徴とする半導体装置。
JP1987192376U 1987-12-17 1987-12-17 半導体装置 Expired - Lifetime JP2529366Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987192376U JP2529366Y2 (ja) 1987-12-17 1987-12-17 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987192376U JP2529366Y2 (ja) 1987-12-17 1987-12-17 半導体装置

Publications (2)

Publication Number Publication Date
JPH0195760U true JPH0195760U (ja) 1989-06-26
JP2529366Y2 JP2529366Y2 (ja) 1997-03-19

Family

ID=31483238

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987192376U Expired - Lifetime JP2529366Y2 (ja) 1987-12-17 1987-12-17 半導体装置

Country Status (1)

Country Link
JP (1) JP2529366Y2 (ja)

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360U (ja) * 1979-07-04 1981-02-02
JPS5895657U (ja) * 1981-12-23 1983-06-29 日本電気株式会社 集積回路用リ−ドフレ−ム
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5612360U (ja) * 1979-07-04 1981-02-02
JPS5895657U (ja) * 1981-12-23 1983-06-29 日本電気株式会社 集積回路用リ−ドフレ−ム
JPS58143541A (ja) * 1982-02-22 1983-08-26 Hitachi Ltd 半導体装置

Also Published As

Publication number Publication date
JP2529366Y2 (ja) 1997-03-19

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