JPH01107132U - - Google Patents
Info
- Publication number
- JPH01107132U JPH01107132U JP1988002272U JP227288U JPH01107132U JP H01107132 U JPH01107132 U JP H01107132U JP 1988002272 U JP1988002272 U JP 1988002272U JP 227288 U JP227288 U JP 227288U JP H01107132 U JPH01107132 U JP H01107132U
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- input
- external wiring
- wiring terminal
- semiconductor element
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
- H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
- H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
- H10W70/68—Shapes or dispositions thereof
- H10W70/682—Shapes or dispositions thereof comprising holes having chips therein
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W72/00—Interconnections or connectors in packages
- H10W72/50—Bond wires
- H10W72/531—Shapes of wire connectors
- H10W72/5363—Shapes of wire connectors the connected ends being wedge-shaped
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Parts Printed On Printed Circuit Boards (AREA)
- Semiconductor Integrated Circuits (AREA)
Description
第１図は本考案の半導体装置の一実施例を示す
斜視図、第２図は第１図の要部拡大平面図、第３
図は第２図のＡ―Ａ断面図、第４図は従来の半導
体装置の斜視図、第５図は第４図の要部拡大平面
図である。 ２……半導体素子、３ａ，３ｂ……外部配線端
子、４ａ，４ｂ……入出力用端子、５……ボンデ
イングワイヤ、６……電源用パターン、７……バ
イアス素子。
斜視図、第２図は第１図の要部拡大平面図、第３
図は第２図のＡ―Ａ断面図、第４図は従来の半導
体装置の斜視図、第５図は第４図の要部拡大平面
図である。 ２……半導体素子、３ａ，３ｂ……外部配線端
子、４ａ，４ｂ……入出力用端子、５……ボンデ
イングワイヤ、６……電源用パターン、７……バ
イアス素子。
Claims (1)
- 複数の入出力用端子を有する半導体素子と外部
配線端子とがボンデイングワイヤにより電気接続
される半導体装置において、前記外部配線端子の
電源用パターンに一端が接続され、前記半導体素
子の入出力用端子に他端が選択的に接続されるバ
イアス素子を備えたことを特徴とする半導体装置
。
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988002272U JPH01107132U (ja) | 1988-01-12 | 1988-01-12 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1988002272U JPH01107132U (ja) | 1988-01-12 | 1988-01-12 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH01107132U true JPH01107132U (ja) | 1989-07-19 |
Family
ID=31202894
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1988002272U Pending JPH01107132U (ja) | 1988-01-12 | 1988-01-12 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01107132U (ja) |
-
1988
- 1988-01-12 JP JP1988002272U patent/JPH01107132U/ja active Pending