JPH0265339U - - Google Patents

Info

Publication number
JPH0265339U
JPH0265339U JP1988144887U JP14488788U JPH0265339U JP H0265339 U JPH0265339 U JP H0265339U JP 1988144887 U JP1988144887 U JP 1988144887U JP 14488788 U JP14488788 U JP 14488788U JP H0265339 U JPH0265339 U JP H0265339U
Authority
JP
Japan
Prior art keywords
electrode
pads
wiring board
semiconductor chip
connection structure
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988144887U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988144887U priority Critical patent/JPH0265339U/ja
Publication of JPH0265339U publication Critical patent/JPH0265339U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5445—Dispositions of bond wires being orthogonal to a side surface of the chip, e.g. parallel arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H10W72/932—Plan-view shape, i.e. in top view

Landscapes

  • Wire Bonding (AREA)

Description

【図面の簡単な説明】
第1図は本考案の一実施例に係る電極接続構造
の要部を示す拡大平面図、第2図は全体の平面図
、第3図は従来例に係る配線基板側の平面図、第
4図はワイヤボンデイング性に関する実験の説明
図、第5図はその実験結果の特性図である。 1……配線基板、3,6……電極パツド、4…
…電極、6……半導体チツプ。

Claims (1)

    【実用新案登録請求の範囲】
  1. 電極パツドの対応するものどうしをワイヤボン
    デイングして、可撓性の配線基板と半導体チツプ
    を電気的に接続する電極接続構造において、配線
    基板の電極パツドに、半導体チツプに向けて延出
    した幅狭の電極を形成したことを特徴とする電極
    接続構造。
JP1988144887U 1988-11-08 1988-11-08 Pending JPH0265339U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988144887U JPH0265339U (ja) 1988-11-08 1988-11-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988144887U JPH0265339U (ja) 1988-11-08 1988-11-08

Publications (1)

Publication Number Publication Date
JPH0265339U true JPH0265339U (ja) 1990-05-16

Family

ID=31412991

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988144887U Pending JPH0265339U (ja) 1988-11-08 1988-11-08

Country Status (1)

Country Link
JP (1) JPH0265339U (ja)

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