JPH0450760B2 - - Google Patents
Info
- Publication number
- JPH0450760B2 JPH0450760B2 JP62286205A JP28620587A JPH0450760B2 JP H0450760 B2 JPH0450760 B2 JP H0450760B2 JP 62286205 A JP62286205 A JP 62286205A JP 28620587 A JP28620587 A JP 28620587A JP H0450760 B2 JPH0450760 B2 JP H0450760B2
- Authority
- JP
- Japan
- Prior art keywords
- conductive pattern
- resin
- metal foil
- coat film
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000011347 resin Substances 0.000 claims description 34
- 229920005989 resin Polymers 0.000 claims description 34
- 239000011888 foil Substances 0.000 claims description 17
- 229910052751 metal Inorganic materials 0.000 claims description 17
- 239000002184 metal Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 15
- 238000005530 etching Methods 0.000 claims description 7
- 238000009713 electroplating Methods 0.000 claims description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 15
- 239000011889 copper foil Substances 0.000 description 12
- 239000010410 layer Substances 0.000 description 7
- PXHVJJICTQNCMI-UHFFFAOYSA-N Nickel Chemical compound [Ni] PXHVJJICTQNCMI-UHFFFAOYSA-N 0.000 description 4
- 238000004519 manufacturing process Methods 0.000 description 4
- 239000004065 semiconductor Substances 0.000 description 4
- 229910052802 copper Inorganic materials 0.000 description 3
- 239000010949 copper Substances 0.000 description 3
- 239000011229 interlayer Substances 0.000 description 3
- 238000000034 method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 239000000919 ceramic Substances 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 229910052759 nickel Inorganic materials 0.000 description 2
- 238000007747 plating Methods 0.000 description 2
- 229920001721 polyimide Polymers 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 238000007772 electroless plating Methods 0.000 description 1
- 239000003822 epoxy resin Substances 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 229920002120 photoresistant polymer Polymers 0.000 description 1
- 229920000647 polyepoxide Polymers 0.000 description 1
- 239000009719 polyimide resin Substances 0.000 description 1
- 238000004080 punching Methods 0.000 description 1
Landscapes
- Production Of Multi-Layered Print Wiring Board (AREA)
Description
【発明の詳細な説明】
(イ) 産業上の利用分野
本発明は多層配線基板の製造方法に関し、特に
第2層目の導電パターンの形成を改良した多層配
線基板の製造方法に関する。DETAILED DESCRIPTION OF THE INVENTION (a) Field of Industrial Application The present invention relates to a method for manufacturing a multilayer wiring board, and particularly to a method for manufacturing a multilayer wiring board in which the formation of a second layer conductive pattern is improved.
(ロ) 従来の技術
従来の多層配線基板の製造方法を第2図A乃至
第2図Cを参照して説明する。(b) Prior Art A conventional method for manufacturing a multilayer wiring board will be described with reference to FIGS. 2A to 2C.
先ず第2図Aに示す如く、絶縁基板11上に第
1の導電パターン12を形成する。絶縁基板11
としてはセラミツクス等を用い、基板11全面に
銅箔を貼着した後所望のパターンにエツチングし
て形成される。 First, as shown in FIG. 2A, a first conductive pattern 12 is formed on an insulating substrate 11. Insulating substrate 11
It is formed by using ceramics or the like as a material, and by adhering copper foil to the entire surface of the substrate 11 and then etching it into a desired pattern.
続いて第2図Bに示す如く、第1の導電パター
ン12を被覆する様に層間絶縁膜13を形成し、
所望の第1の導電パターン12上にスルーホール
14を形成している。層間絶縁膜13としてはポ
リイミド層あるいは永久ホトレジスト層等を用い
る。 Subsequently, as shown in FIG. 2B, an interlayer insulating film 13 is formed to cover the first conductive pattern 12,
A through hole 14 is formed on a desired first conductive pattern 12. As the interlayer insulating film 13, a polyimide layer, a permanent photoresist layer, or the like is used.
更に第2図Cに示す如く、層間絶縁膜13上に
無電解銅又はニツケルメツキにより第2の導電パ
ターン15を形成する。第2の導電パターン15
はスルーホール14を介して第1の導電パターン
12と接続され、多層構造を実現する。 Furthermore, as shown in FIG. 2C, a second conductive pattern 15 is formed on the interlayer insulating film 13 by electroless copper or nickel plating. Second conductive pattern 15
is connected to the first conductive pattern 12 via the through hole 14 to realize a multilayer structure.
なお斯る多層配線基板の製造方法は特開昭60−
10697号に開示されている。 The method for manufacturing such a multilayer wiring board is disclosed in Japanese Patent Application Laid-Open No. 1986-
No. 10697.
(ハ) 発明が解決しようとする問題点
斯上の従来の方法では第2の導電パターンを銅
又はニツケルの無電解メツキで形成するので導電
路とするために厚さを30μ以上に形成するのに24
時間以上要する問題点があつた。(c) Problems to be solved by the invention In the above conventional method, the second conductive pattern is formed by electroless plating of copper or nickel, so it must be formed to have a thickness of 30 μm or more in order to form a conductive path. to 24
There was a problem that required more time.
(ニ) 問題点を解決するための手段
本発明は上述した問題点に鑑みて為されたもの
であり、絶縁基板上に第1の導電パターンを形成
する工程と、第1の導電パターン上に導電パター
ンの一部分を囲む樹脂コート膜を形成する工程
と、樹脂コート膜に対応する開口部及びバイアホ
ール用の孔を金属箔付き樹脂層に設けた後、金属
箔付き樹脂層を第1の導電パターン上に貼着する
工程と、バイアホールに電気メツキを施し第1の
導電パターンと前記金属箔とを接続する工程と、
金属箔とエツチングして第2の導電パターンを形
成する工程とを具備して解決する。(d) Means for solving the problems The present invention has been made in view of the above-mentioned problems, and includes a step of forming a first conductive pattern on an insulating substrate, and a step of forming a first conductive pattern on the first conductive pattern. After forming a resin coat film that surrounds a part of the conductive pattern and providing openings and holes for via holes corresponding to the resin coat film in the resin layer with metal foil, the resin layer with metal foil is coated with a first conductive layer. a step of pasting it on the pattern; a step of electroplating the via hole to connect the first conductive pattern and the metal foil;
The present invention is solved by including a step of forming a second conductive pattern by etching the metal foil.
(ホ) 作用
この様に本発明に依れば第1の導電パターン上
にパターンの一部分を囲む樹脂コート膜を形成
し、樹脂コート膜に対応する開口部及びバイアホ
ール用の孔を金属箔付き樹脂に設けて第1の導電
パターン上に貼着することにより、金属箔をエツ
チングして第2の導電パターンを形成することが
でき短時間で第2の導電パターンを形成すること
ができる。(E) Effect As described above, according to the present invention, a resin coat film surrounding a part of the pattern is formed on the first conductive pattern, and the openings and via holes corresponding to the resin coat film are coated with metal foil. By providing the metal foil on resin and pasting it on the first conductive pattern, the second conductive pattern can be formed by etching the metal foil, and the second conductive pattern can be formed in a short time.
(ヘ) 実施例
以下に第1図A乃至第1図Hに示した実施例に
基づいて本発明を詳細に説明する。(F) Embodiments The present invention will be described in detail below based on the embodiments shown in FIGS. 1A to 1H.
先ず第1図Aに示す如く、絶縁基板1上に第1
の導電パターン2を形成する。絶縁基板1として
はセラミツクスあるいは表面を酸化膜で被覆した
アルミニウム等を用い、第1の導電パターン2は
基板1全面に銅箔を貼着した後所望のパターンに
エツチングして形成される。 First, as shown in FIG. 1A, a first
A conductive pattern 2 is formed. The insulating substrate 1 is made of ceramics or aluminum whose surface is coated with an oxide film, and the first conductive pattern 2 is formed by pasting copper foil over the entire surface of the substrate 1 and then etching it into a desired pattern.
次に第1図Bに示す如く、第1の導電パターン
2上に第1の導電パターン2の一部分を囲む樹脂
コート膜3を形成する。樹脂コート膜3は、エポ
キシ樹脂等の樹脂を第1の導電パターン2と重畳
する様に印刷形成する。即ち、第1の導電パター
ン2の半導体素子が固着されるパツド2′の周囲
の第1の導電パターン2と重畳する様に且つ半導
体素子が固着されるパツド2′の周囲を囲む様枠
状に形成する。樹脂コート膜3の厚み及び幅は任
意に選択することができ本実施例では厚みは
15μ、幅は約1.5mmに形成するものとする。 Next, as shown in FIG. 1B, a resin coat film 3 surrounding a portion of the first conductive pattern 2 is formed on the first conductive pattern 2. Then, as shown in FIG. The resin coat film 3 is formed by printing a resin such as epoxy resin so as to overlap the first conductive pattern 2 . That is, the first conductive pattern 2 is formed in a frame shape so as to overlap with the first conductive pattern 2 around the pad 2' to which the semiconductor element is fixed, and to surround the periphery of the pad 2' to which the semiconductor element is fixed. Form. The thickness and width of the resin coat film 3 can be arbitrarily selected, and in this example, the thickness is
It shall be formed with a thickness of 15μ and a width of approximately 1.5mm.
次に第1図Cに示す如く、樹脂コート膜3に対
応する開口部4及びバイアホール用の孔5を金属
箔付き樹脂6に設けた後、金属箔付き樹脂層6を
絶縁基板1上に貼着する。金属箔付き樹脂6はポ
リイミド樹脂等の絶縁樹脂8と銅箔7とが一体化
された、いわゆるフレキシブルシートを用いる。
この金属箔付き樹脂6にはあらかじめパンチング
等により、枠状に形成された樹脂コート膜3と対
応する開口部4及び第1の導電パターン2と多層
配線するためのバイアホール用の孔5が形成され
ており、基板1全面上に熱圧着する。このとき金
属箔付き樹脂6の開口部4内の終端辺は樹脂コー
ト3上の中央付近に位置する様に考慮する。 Next, as shown in FIG. 1C, after providing an opening 4 corresponding to the resin coat film 3 and a hole 5 for a via hole in the resin 6 with metal foil, the resin layer 6 with metal foil is placed on the insulating substrate 1. Paste. As the resin 6 with metal foil, a so-called flexible sheet in which an insulating resin 8 such as a polyimide resin and a copper foil 7 are integrated is used.
In this resin 6 with metal foil, an opening 4 corresponding to the frame-shaped resin coat film 3 and a hole 5 for a via hole for multilayer wiring with the first conductive pattern 2 are formed in advance by punching or the like. It is bonded by thermocompression onto the entire surface of the substrate 1. At this time, consideration is given so that the end edge of the resin 6 with metal foil inside the opening 4 is located near the center on the resin coat 3.
次に第1図Dに示す如く、基板1上にドライフ
イルム9を約80〜100℃で熱圧着して基板1全面
に付着する。 Next, as shown in FIG. 1D, a dry film 9 is thermocompressed onto the substrate 1 at about 80 DEG to 100 DEG C. to adhere to the entire surface of the substrate 1.
次に第1図Eに示す如く、多層配線用の孔5及
び周辺のドライフイルム9を写真蝕刻法により除
去しバイアホールを形成する。 Next, as shown in FIG. 1E, the multilayer wiring hole 5 and the surrounding dry film 9 are removed by photolithography to form a via hole.
次に第1図Fに示す如く、バイアホールに電気
メツキを施し、第1の導電パターン2と銅箔7と
を接続する。 Next, as shown in FIG. 1F, the via hole is electroplated to connect the first conductive pattern 2 and the copper foil 7.
第1図Eの如く、バイアホール及びバイアホー
ルの周辺の銅箔7は露出され、銅の無電解メツキ
を行い、第1の導電パターン2と銅箔7とを接続
して、残りのドライフイルム9を除去する。 As shown in FIG. 1E, the via hole and the copper foil 7 around the via hole are exposed, electroless copper plating is performed, the first conductive pattern 2 and the copper foil 7 are connected, and the remaining dry film is removed. Remove 9.
次に第1図G及び第1図Hに示す如く、銅箔7
をエツチングして第2の導電パターン10を形成
する。ドライフイルム除去後、再び絶縁基板1全
面にドライフイルムを熱圧着して写真蝕刻法によ
り、第1図Gの如く、第2の導電パターン10と
なる銅箔7上及び樹脂コート膜3内の第1の導電
パターン2上のみにドライフイルム9′を残して
他の部分を除去した後、銅箔7をエツチングする
ことにより、第1図Hの如く、第1の導電パター
ン2上に第2の導電パターン10を形成すること
ができる。即ち、第1図Iに示す如く、半導体素
子が固着されるパツド2′は枠状の樹脂コート膜
3によつて囲まれ、その囲まれた領域内には第1
の導電パターン2の先端部がパツド2′の近傍ま
で延在形成される。そして、パツド2′上には、
図示されないが、半導体素子が固着され、周辺の
第1の導電パターン2と接続される。 Next, as shown in FIGS. 1G and 1H, the copper foil 7
A second conductive pattern 10 is formed by etching. After removing the dry film, the dry film is thermocompression bonded to the entire surface of the insulating substrate 1 again, and photolithography is applied to form the second conductive pattern 10 on the copper foil 7 and in the resin coat film 3, as shown in FIG. 1G. After leaving the dry film 9' only on the first conductive pattern 2 and removing the other parts, the copper foil 7 is etched to form the second conductive pattern 2 on the first conductive pattern 2, as shown in FIG. 1H. A conductive pattern 10 can be formed. That is, as shown in FIG. 1I, the pad 2' to which the semiconductor element is fixed is surrounded by a frame-shaped resin coat film 3, and the first pad 2' is surrounded by a frame-shaped resin coat film 3.
The tip of the conductive pattern 2 is formed to extend to the vicinity of the pad 2'. And on pad 2',
Although not shown, a semiconductor element is fixed and connected to the first conductive pattern 2 in the periphery.
第1図Gに示した工程において、樹脂コート膜
3内の第1の導電パターン2上にドライフイルム
9′を残す場合、写真蝕刻法により微細加工に形
成することができるが、マスクの位置ズレ等でド
ライフイルム9′と絶縁樹脂8との間に微小に隙
間が発生し銅箔エツチング時に隙間からエツチヤ
ントが入り第1の導電パターン2を蝕刻する恐れ
があるが本発明では樹脂コート膜3が形成されて
いるので第1の導電パターン2が蝕刻される恐れ
はない。 In the step shown in FIG. 1G, if the dry film 9' is left on the first conductive pattern 2 in the resin coat film 3, it can be formed in a fine pattern by photolithography; etc., a minute gap is generated between the dry film 9' and the insulating resin 8, and when etching the copper foil, there is a risk that etchant may enter through the gap and etch the first conductive pattern 2. However, in the present invention, the resin coat film 3 is Therefore, there is no fear that the first conductive pattern 2 will be etched.
(ト) 発明の効果
以上に詳述した如く、本発明に依れば、第2の
導電パターンを銅箔により形成することができ、
第2の導電パターンの断線を防止することができ
る。(g) Effects of the invention As detailed above, according to the present invention, the second conductive pattern can be formed of copper foil,
Disconnection of the second conductive pattern can be prevented.
また本発明では開口部が設けられているため、
第1の導電パターン上に回路素子を固着すること
ができるので、熱抵抗を損なうことなく発熱を有
する回路素子を搭載することができる。 Further, in the present invention, since an opening is provided,
Since the circuit element can be fixed onto the first conductive pattern, a circuit element that generates heat can be mounted without impairing thermal resistance.
第1図A乃至第1図Iは本発明の実施例を示す
断面図および平面図、第2図A乃至第2図Cは従
来例を示す断面図である。
1……絶縁基板、2……第1の導電パターン、
3……樹脂コート膜、4……開口部、5……孔、
6……金属箔付き樹脂、7……銅箔、8……絶縁
樹脂、9,9′……ドライフイルム、10……第
2の導電パターン。
1A to 1I are sectional views and plan views showing an embodiment of the present invention, and FIGS. 2A to 2C are sectional views showing a conventional example. 1... Insulating substrate, 2... First conductive pattern,
3... Resin coat film, 4... Opening, 5... Hole,
6... Resin with metal foil, 7... Copper foil, 8... Insulating resin, 9, 9'... Dry film, 10... Second conductive pattern.
Claims (1)
工程と、 前記第1の導電パターン上に前記パターンの一
部を囲む樹脂コート膜を枠状に形成する工程と、 前記樹脂コート膜に囲まれた領域に対応する開
口部およびバイアホール用の孔を金属箔付き樹脂
層に設けた後、前記金属箔付き樹脂層を前記絶縁
基板上に貼着する工程と、 前記孔に電気メツキを施してバイアホールを形
成し前記第1の導電パターンと前記金属箔とを接
続する工程と、 前記基板上にレジスト膜を形成し、少なくとも
前記樹脂コート膜に重畳させた開口部領域および
バイアホール上に前記レジスト膜を残存させ、金
属箔をエツチングし第2の導電パターンを形成す
る工程とを具備することを特徴とする多層配線基
板の製造方法。[Scope of Claims] 1. A step of forming a first conductive pattern on an insulating substrate; A step of forming a frame-shaped resin coat film surrounding a part of the pattern on the first conductive pattern; After providing an opening corresponding to an area surrounded by a resin coat film and a hole for a via hole in the resin layer with metal foil, adhering the resin layer with metal foil onto the insulating substrate; forming a via hole by electroplating to connect the first conductive pattern and the metal foil; forming a resist film on the substrate, and forming an opening region overlapping at least the resin coat film; and a step of leaving the resist film on the via hole and etching the metal foil to form a second conductive pattern.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62286205A JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62286205A JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01128493A JPH01128493A (en) | 1989-05-22 |
| JPH0450760B2 true JPH0450760B2 (en) | 1992-08-17 |
Family
ID=17701327
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62286205A Granted JPH01128493A (en) | 1987-11-12 | 1987-11-12 | Manufacture of multilayer interconnection substrate |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH01128493A (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH0744322B2 (en) * | 1989-06-02 | 1995-05-15 | 松下電工株式会社 | Circuit board |
| JPH0756912B2 (en) * | 1991-01-28 | 1995-06-14 | 松下電工株式会社 | Method for manufacturing multilayer circuit board |
-
1987
- 1987-11-12 JP JP62286205A patent/JPH01128493A/en active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPH01128493A (en) | 1989-05-22 |
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