JPH0173936U - - Google Patents
Info
- Publication number
- JPH0173936U JPH0173936U JP1987170367U JP17036787U JPH0173936U JP H0173936 U JPH0173936 U JP H0173936U JP 1987170367 U JP1987170367 U JP 1987170367U JP 17036787 U JP17036787 U JP 17036787U JP H0173936 U JPH0173936 U JP H0173936U
- Authority
- JP
- Japan
- Prior art keywords
- melting point
- element connection
- utility
- registration request
- low melting
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
- H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
- Lead Frames For Integrated Circuits (AREA)
Description
第1図は本考案に係るハイブリツドIC基板の
第1実施例を示す断面図、第2図は同平面図、第
3図は第2実施例を示す断面図、第4図はハイブ
リツドICの断面図、第5図〜第7図は従来例を
示す断面図である。
A…ハイブリツドIC基板、10…基板、11
…配線リード、11a…素子接続部、12…バン
プ。
Fig. 1 is a sectional view showing a first embodiment of a hybrid IC board according to the present invention, Fig. 2 is a plan view thereof, Fig. 3 is a sectional view showing the second embodiment, and Fig. 4 is a sectional view of the hybrid IC. 5 to 7 are cross-sectional views showing conventional examples. A... Hybrid IC board, 10... Substrate, 11
... Wiring lead, 11a... Element connection part, 12... Bump.
Claims (1)
に、低融点金属で成るバンプを形成したことを特
徴とする混成集積回路基板。 1. A hybrid integrated circuit board characterized in that bumps made of a low melting point metal are formed at the element connection portions of wiring leads to which circuit elements are connected.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170367U JPH0173936U (en) | 1987-11-07 | 1987-11-07 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1987170367U JPH0173936U (en) | 1987-11-07 | 1987-11-07 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0173936U true JPH0173936U (en) | 1989-05-18 |
Family
ID=31461243
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1987170367U Pending JPH0173936U (en) | 1987-11-07 | 1987-11-07 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0173936U (en) |
-
1987
- 1987-11-07 JP JP1987170367U patent/JPH0173936U/ja active Pending
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