JPH01143146U - - Google Patents

Info

Publication number
JPH01143146U
JPH01143146U JP1988039828U JP3982888U JPH01143146U JP H01143146 U JPH01143146 U JP H01143146U JP 1988039828 U JP1988039828 U JP 1988039828U JP 3982888 U JP3982888 U JP 3982888U JP H01143146 U JPH01143146 U JP H01143146U
Authority
JP
Japan
Prior art keywords
lead
portions
frame
semiconductor device
chip
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP1988039828U
Other languages
English (en)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988039828U priority Critical patent/JPH01143146U/ja
Publication of JPH01143146U publication Critical patent/JPH01143146U/ja
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/5449—Dispositions of bond wires not being orthogonal to a side surface of the chip, e.g. fan-out arrangements
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Lead Frames For Integrated Circuits (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)

Description

【図面の簡単な説明】
第１図はこの考案の一実施例であるジグザグ・
インライン方式の半導体装置の斜視図、第２図は
その正面図、第３図ないし第８図はこの考案のそ
れぞれ異なる実施例を示す側面図ないし斜視図、
第９図は本考案のさらに他の実施例の部分的断面
図、第１０図は従来のジグザグ・インライン方式
の半導体装置の斜視図、第１１図はその側面図で
ある。 １１：半導体チツプ、１２：支持フレーム、１
３，１４，１５，１６，１７，１８：リードフレ
ーム、１３ａ，１４ａ，１５ａ，１６ａ，１７ａ
，１８ａ：インナーリード部、１３ｂ，１４ｂ，
１５ｂ，１６ｂ，１７ｂ，１８ｂ：リード端子部
、１９：接続線（金線）、２０：封止体、２１：
接着剤（接着部）。

Claims (1)

    【実用新案登録請求の範囲】
  1. 半導体チツプが取り付けられる支持フレームと
    、インナーリード部とリード端子部を持ち前記チ
    ツプとインナーリード部がワイヤボンデイングさ
    れる複数枚のリードフレームと、前記リード端子
    部を除いたリードフレーム、半導体チツプならび
    に支持フレームを気密に封ずる封止体とを備えた
    半導体装置において、前記複数枚のリードフレー
    ムの少なくとも一部が、インナーリード部とリー
    ド端子部の中間において、絶縁性の接着剤により
    相互に接着されていることを特徴とする半導体装
    置。
JP1988039828U 1988-03-25 1988-03-25 Pending JPH01143146U (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988039828U JPH01143146U (ja) 1988-03-25 1988-03-25

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988039828U JPH01143146U (ja) 1988-03-25 1988-03-25

Publications (1)

Publication Number Publication Date
JPH01143146U true JPH01143146U (ja) 1989-10-02

Family

ID=31266317

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988039828U Pending JPH01143146U (ja) 1988-03-25 1988-03-25

Country Status (1)

Country Link
JP (1) JPH01143146U (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59224152A (ja) * 1983-06-03 1984-12-17 Nec Ic Microcomput Syst Ltd 集積回路装置

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59224152A (ja) * 1983-06-03 1984-12-17 Nec Ic Microcomput Syst Ltd 集積回路装置

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