JPH01150367A - Manufacture of junction type fet - Google Patents

Abstract

PURPOSE:To realize a short gate length and to manufacture a high-speed JFET by etching a lower semiconductor layer with the metal stripe of a gate electrode as a mask, and forming a gate. CONSTITUTION:An n-type InGaAsP layer is caused to grow as a channel layer 2, a p-type InP layer 31 and a p-type InGaAsP layer 32 are caused to grow as a gate forming semiconductor layer on an SI-InP substrate 1, and a gate electrode 4 is formed. Then, with the electrode 4 as a mask the layer 32 is etched with mixture solution of sulfuric acid and hydrogen peroxide water thereby to form a gate 32A as an upper layer. In this case, the length of the gate can be made shorter than the gate electrode 4 by a side etching effect. Then, the layer 31 is etched thereby to form a gate 31A as a lower layer. Further, a metal material for source, drain electrodes is deposited directly on the substrate, a metal layer except a predetermined region is removed, and source, drain electrodes 5, 6 are formed.

Description

DETAILED DESCRIPTION OF THE INVENTION [Summary] This invention relates to a method for manufacturing a junction field effect transistor (JPET).

The purpose of this method is to enable the formation of a gate by etching the underlying semiconductor layer using the metal stripe of the gate electrode as a mask, thereby realizing a short gate length and increasing the speed of JPET.

A first semiconductor layer and a second semiconductor layer thinner than the core layer are sequentially formed on the channel layer.
A semiconductor layer is grown, a gate metal electrode is formed thereon, and the second semiconductor layer is selectively etched using the gate metal electrode as a mask to expose the first semiconductor layer. The method includes a step of selectively etching the first semiconductor layer using the electrode and the second semiconductor layer as a mask to expose the channel layer.

When the channel layer is made of n-type InGaAsP, and the first semiconductor layer is made of InP and the second semiconductor layer is made of InGaAsP, the second semiconductor layer is made of a mixed solution containing sulfuric acid and hydrogen peroxide, and the first semiconductor layer is made of InGaAsP. is configured to be etched with hydrochloric acid.

[Industrial application field]

The present invention relates to a method for manufacturing a junction field effect transistor.

JFET is used as a driving element for optical semiconductor devices.

[Conventional technology]

In order to improve the high-speed performance of JPET, it is effective to shorten the gate length.

Conventionally, the technique shown in FIG. 2 has been used to form short gates1).

1) J. Cheng and S. R. Forres
t+High 5peed Ina, 53Gaa, nt
AS/InP JunctionField-effe
ct Transistor for Optoele
ctronicIntegration, in Op
t, Fiber Commun, Conf.

Tech, Digest, Feb; 11-13.
1985. FIG. 2<1) to (3) are cross-sectional views illustrating a conventional gate forming method.

In FIG. 2 (1), an n-type 1nP (n-1nP) channel layer 2 is formed on a semi-insulating (SI)-InP substrate 1.
p-type TnGaAsP (p-1
(nGaAsP) layer 3 is grown.

Next, a gate electrode 4 made of metal (eg, Au/Pt/Ti) stripes is formed.

In FIG. 2(2), the InGaAsP layer 3 for gate formation is chemically etched using the gate electrode 4 as a mask to form a gate layer 3A.

At this time, the gate length can be made shorter than the gate electrode 4 due to the effect of side etching.

In FIG. 2(3), a metal material (Au/AuGe) for the source and drain electrodes is deposited from directly above the substrate, and a lift-off process is used to remove the metal layer other than a predetermined area, and the source and drain electrodes 5.6 form.

In this method, the gate and source/drain electrodes are insulated by the eaves of the gate electrode and the thickness of the gate.

[Problem that the invention seeks to solve]

In the conventional example, when etching the InGaAsP layer 3 for gate formation using the gate electrode 4 as a mask.

This is because the etching rate at the interface with the mask is high.

If the gate layer thickness is large, a problem arises in that the gate electrode 4 is peeled off before the channel layer is exposed, as shown in FIG.

[Means for solving problems]

The solution to the above problem is to grow a first semiconductor layer and a second semiconductor layer thinner than the core layer in order on the channel layer, form a gate metal electrode thereon, and use the gate metal electrode as a mask to form a second semiconductor layer. The second semiconductor layer is selectively etched to expose the first semiconductor layer. Next, the first semiconductor layer is selectively etched using the gate metal electrode and the second semiconductor layer as a mask to form a channel layer. Joining type F with exposed process
This is achieved by the ET manufacturing method.

When the channel layer is made of n-type InGaAsP, the first semiconductor layer is made of TnP, and the second semiconductor layer is made of TnGaAsP, the second semiconductor layer 1nGaAsP is mixed with a mixture containing sulfuric acid and hydrogen peroxide, and the first semiconductor layer is made of n-type InGaAsP. Etch the TnP layer with hydrochloric acid.

[Effect]

In the present invention, the gate has a 2N structure, and the etching rate at the interface between the metal of the gate electrode and the semiconductor of the gate is particularly high, so it is necessary to shorten the etching time. Furthermore, since the gate needs to be thick enough to be insulated from the source and drain electrodes as described above, the thickness is compensated for by the underlying semiconductor layer.

When etching a two-layer gate, choose an etchant for the lower layer that will not etch the upper layer.

Since the lower layer in the area directly below the upper layer is not side-etched, a gate with an ideal cross-sectional shape can be obtained.

〔Example〕

FIGS. 11-(5) are a sectional view and a plan view illustrating a gate forming method according to an embodiment of the present invention.

A p-1nP layer 31 as a body layer and a p-1nGaAsP as a second semiconductor layer (emission wavelength composition 1.3.crm
) growing layer 32;

The specifications of each semiconductor layer are as follows.

Drawing number Layer F-bu concentration Thickness (cm-
') (person) 2 n-1nGaAsF Sn IE17
1000-200031 p-1nP Cd
51E17 3500-500032
p-1nGaAsP Zn IE19
3500-5000 1 For example 1 width 1 μm, thickness 1
μm10.1μm70.1μm Au/Pt/Ti
A gate electrode 4 consisting of a metal stripe formed in layers is formed.

In FIG. 1(2), with the gate electrode 4 as a mask, I
The nGaAsP layer 32 is etched with a mixture of sulfuric acid and hydrogen peroxide to form the upper gate 32A.

At this time, the gate length can be made shorter than the gate electrode 4 due to the effect of side etching.

In FIG. 1(3), the InP layer 31 is etched with hydrochloric acid to form the lower gate 31A.

At this time, since the lower side of the gate 32A is not side-etched, a gate having an ideal cross-sectional shape as shown in FIG. 1 can be obtained.

In Figure 1 (4), 300 layers of Au/metal material for source/drain electrodes (thickness: 2000 layers) are measured from just above the substrate.
Then, a lift-off process is used to remove the metal layer except for a predetermined region, thereby forming a source/drain electrode 5.6.

FIG. 1(5) is a plan view.

〔Effect of the invention〕

As explained above, according to the present invention, the underlying semiconductor layer can be etched using the metal stripe of the gate electrode as a mask.

Therefore, if the metal stripe is formed with the minimum width of lithography technology, the gate length can be further shortened.
JPET speed can be increased.

[Brief explanation of the drawing]

11-(5) are a sectional view and a plan view illustrating a gate forming method according to an embodiment of the present invention. FIG. 2 fil-(3) is a sectional view illustrating a conventional gate forming method. FIG. 3 is a sectional view illustrating the problem. In fig. 1 is a 5l-1nP substrate. 2 is a channel J layer 2, which is an n-1nGaAsF layer. 31 is a first semiconductor layer, which is a p-1nP layer. 32 is a second semiconductor layer, which is a p-InGaAsP layer. 31A is a lower layer gate, and 32A is an upper layer gate. 4 is a gate electrode made of Au/Pt/Ti layer. 5.6 is a source/drain electrode, and a sub-embodiment of the Au/AuGe layer embodiment = P side view $1 Figure (5) Thousand-sided view

Claims (2)

[Claims] (1) A first semiconductor layer and a second semiconductor layer thinner than the first semiconductor layer are grown in order on the channel layer, a gate metal electrode is formed thereon, and the second semiconductor layer is grown using the gate metal electrode as a mask. selectively etching to expose the first semiconductor layer, and then selectively etching the first semiconductor layer using the gate metal electrode and the second semiconductor layer as a mask to expose the channel layer. A method for manufacturing a junction FET, comprising: (2) The channel layer is made of n-type InGaAsP, the first semiconductor layer is made of InP, and the second semiconductor layer is made of InGaAsP, and the second semiconductor layer is made of a mixed solution containing sulfuric acid and hydrogen peroxide, and the first semiconductor layer is made of A method for manufacturing a junction FET according to claim 1, characterized in that the layer is etched with hydrochloric acid.