JPS6362048A - System for registering execution history of microprogram - Google Patents

Abstract

PURPOSE:To reduce the cost of the titled system by effectively utilizing an idle area of a main memory as a trace memory. CONSTITUTION:When a load program stored in a ROM 5 is started, a microprogram in a main memory 3 is inputted to a controller 1 via a system bus 1000 and also to a RAM 6 serving as a main memory via a data bus 100. The controller 1 is actuated with execution of an action control microprogram stored in the RAM 6 and each microinstruction is read out to an instruction register 16. Then a microcommand CMD decoded by a decoder 18 is carried out by an executing part (not shown here). When a register indication 51 is given to the register indicating information on the microinstruction read out of the RAM 6, a trap control circuit 7 produces an interruption indicating signal 53 and a trap address corresponding to the register indicating information. When a register program is started, a tracing action of the microprogram is started and the collected data on the microprogram are stored in the memory 3.

Description

[Detailed Description of the Invention] (Industrial Application Field) The present invention relates to a microprogram execution history registration method, in particular,
The present invention relates to a microprogram execution history registration method suitable for obtaining various statistical information during microprogram execution, such as the running address distribution of the microprogram and the frequency of microinstructions used during debugging.

(Prior Art) In computer systems, it is common practice to trace and store predetermined information in order to analyze electrical faults that have occurred and to facilitate recovery.0 Conventional microprograms of this type In the execution history registration method, trace information is sequentially stored in a memory called a trace memory, which has a relatively small capacity and employs a circular addressing method.

In this case, the trace information includes the main memory access address, main memory read or write data, operation command signal, common path permission signal, error signal,
Raw data such as the running address of the microprogram and the microinstructions used are selected by designation.

Therefore, in order to obtain the statistical information mentioned above, it is necessary to make sure that the valid information in the trace memory is not lost due to overwriting.
The capacity of the trace memory has been increased, and raw data from the trace memory is read out and analyzed manually.

(Problems to be solved by the invention) In such conventional methods, the amount of hardware increases due to the large capacity of trace memory, and manual analysis work is required to obtain statistical information from raw data. Therefore, there are problems in that it involves mistakes and man-hours.

(Means for Solving Problems) The method of the present invention adds microprogram execution history registration instruction information consisting of multiple bits to a microinstruction, and stores the microprogram together with a plurality of microprogram execution status registration programs in a RAM. The microprogram execution status registration program is selected and executed based on the microprogram execution history registration instruction information that is stored and read together with the microinstructions from the AM. The present invention is characterized in that the execution history of the microprogram is stored in the main memory in an instructed manner. (Example) Next, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing one embodiment of the present invention. Referring to FIG. 1, in this embodiment, a control device 1, a service device 2, and a main storage device 3 are connected by a system bus 1000. However, the system bus 1000 is also connected to a group of devices constituting a computer system, such as an arithmetic unit, an input/output control device, and a magnetic disk control device, which are not shown.

The service device 2 is a device for monitoring and diagnosing the computer system, and includes microprograms and microprograms stored in the RAM 6 (to be described later).
System execution history registration instruction information (hereinafter referred to as registration instruction information) is input into the main storage device 3, and the trap control circuit 7 (described later) is inputted into the main storage device 3.
The n-bit update instruction 50 can be output to the n-bit update instruction 50.

The main storage device 3 temporarily stores the above-mentioned microprograms and registration instruction information, and also stores trace information that is the execution history of the microprograms.

Next, the control device 1 stores the ROM 5 as shown in FIG.
．． RAM6. ) Wrap control circuit 7. Arithmetic circuit 8, +1 adder 10. Address register 11. attack memory 12
．． ± an adder 13, two switchers 14 and 15, and an instruction register 16. Data register 17. Decoder 18.
It consists of a data bus 100 and an address bus 200.

The ROM 5 stores a load program for loading microprograms into the I(, AM 6), and the RAM 6 stores an operation control program for controlling the operation of the control device 1, in which registration instruction information of a multi-bit configuration is added to each microinstruction. A plurality of microprogram execution status registration programs (hereinafter referred to as registration programs) that register programs and trace information in the main memory 3 and an n-bit update program that updates registration instruction information are stored. An example map is shown.

The trap control circuit 7 receives a registration instruction 51 when an abnormality is detected in the control device 1, when an n-bit update instruction 50 is input from the Boubis device 2, or when a registration instruction 51 is included in the registration instruction information of a microinstruction read from the RAM 6. An interrupt instruction signal 53 and a trap address 52 are generated when interrupt processing is performed on a program being executed to change the execution of the program.

The arithmetic circuit 8 performs logical operations, arithmetic operations, etc. in the control device 1, the +1 adder 10 calculates the next microprogram address to be executed, and the address register 11 holds the next microprogram address to be executed. .

The stack memory 12 stores the return address when executing a jump instruction or when processing a trap, and stores the return address at ±7707.
The E unit 13 is an adder for obtaining relative jump destination address information of a conditional jump instruction.

In response to the microcommand CMD output from the decoder 18, the switch 14 selects a jump address 58 specified by the microinstruction itself (in the case of an absolute jump instruction) and a jump address 58 in the case of a success of a conditional jump instruction in the case of a relative address jump instruction. Jump address (output of adder 13 to ±), address at the time of normal instruction execution (output of address register 11)
, return address (output of stack memory 12) or R
One of the AM update addresses 54 is selected, but when the interrupt instruction signal 53 is input, the trap address 52 is switched to be accepted.

In addition, when loading the microprogram into the RAM 6, the switch 15 accepts the output of the OM5, and inputs the output from the RAM 60.
When executing a microprogram, the output of RAM6 is received.

Further, the instruction register 16 holds the micro-instructions read from the RAM 6, the data register 17 holds the micro-instructions read from the RAM 6 and registration instruction information, and the decoder 18 decodes the micro-instructions in the instruction register 16. and generates microcommand CMD.

Next, the operation of this embodiment will be explained.

The operator of this computer system transfers the operation control program of the control device 1 from the main storage device 2 to the main storage device 3.
Load the registration program and n-bit update program in advance. A plurality of bits of registration instruction information is added to each microinstruction of each of these microprograms, and this registration instruction information is used to obtain various statistical information as described above.

When the load program in ROM 5 is started, the microprogram in main memory 3 is transferred to system bus 1000.
to the control device 1 via the data bus 100.
The data is input to the RAM 6 via the .

The RAM update address 54 at this time is supplied from the arithmetic circuit 8 via the address bus 200 and the switch 14.

The control device 1 operates by executing an operation control microprogram in the RAM 5. Each microinstruction is read into the instruction register 16, and the microcommand CMD obtained by decoding in the decoder 18 is executed by an execution unit (not shown). Microcommand CMD is switch 14
is used for input switching control as described above, and is used to determine the address of the next microinstruction.

When the registration instruction 51 is specified in the registration instruction information of the microinstruction read from the RAM 6, the trap control circuit 7 generates an interrupt instruction signal 53 and a trap address 52 corresponding to the registration instruction information. The trap address 52 at this time is the start address of one of the plurality of registered programs.

When this registered program starts functioning, the execution status history (trace information) of the operation control microprogram is sequentially recorded.
It is stored in the main storage device 3. As a specific example of the execution status history, the frequency of access to each area in which the RAM 6 is divided into 100 addresses and the frequency of used microinstructions can be considered.

Furthermore, when the service device 2 inputs the dynamic update data to the main storage device 3 and outputs the n-bit update instruction 50, the trap control circuit 7 generates an interrupt instruction signal 53 and a trap address 52; The address is the start address of the n-pit update program. When the n-bit update program is executed, the registration instruction information in the RAM 5 is updated with the RAM update data in the main storage device 3.

In this way, by storing the n-bit update program in the RAM 6, the registration instruction information can be changed freely, so that more diverse execution status histories can be obtained.

(Effects of the Invention) As described above, the present invention adds registration instruction information to a microinstruction, and stores a registration program whose activation is specified by this registration instruction information in a RAM together with an operation control program. By adopting a configuration in which when the registration instruction information instructs storage of the execution status history of the microprogram, the operation control program is interrupted, the registered program is executed, and the execution status history is stored in the main memory. By simply using a portion of the main memory, which originally has a large capacity and free space, there is no need for a special trace memory as in the past9, and the accuracy of the execution status history is limited by the capacity limit of the trace memory. Also, since the execution status history is created by the registered program, it becomes possible to automatically generate the execution status history as statistical information.

[Brief explanation of drawings]

FIG. 1 shows an embodiment of the present invention, and FIG. 2 shows an example of a RAM map in this embodiment. DESCRIPTION OF SYMBOLS 1...Control device, 2...Service device, 3...Main storage device, 5...ROM, 5...RAM, 7...
Trap control circuit, 8... arithmetic circuit, 10...+1
Adder, 11... Address register, 12... Stack memory, 13... Adder in ±, 14.15...
Switch, 16...Instruction register, 17...Data register, 18...Decoder, 100...Data bus, 200...Address bus, 1000...System bus. Agent Patent Attorney Susumu Uchihara 6＼2-ノ'

Claims (1)

[Scope of Claims] Microprogram execution history registration instruction information consisting of a plurality of bits is added to a microinstruction, and the microprogram is stored in a RAM together with a plurality of microprogram execution status registration programs, and the microprogram is stored in a RAM from the RAM. Selecting and executing the microprogram execution status registration program based on the microprogram execution history registration instruction information read together with the instruction, and executing the microprogram execution status registration program in the manner instructed by the microprogram execution history instruction information. A microprogram execution history registration method characterized in that the execution history of a microprogram is stored in main memory.