JPH0117595B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to an electronic musical instrument, and more particularly to an electronic musical instrument that selectively adds reverberation to a desired series of musical tones among a plurality of musical tones having different tone characteristics such as timbres. Conventionally, electronic musical instruments have been equipped with multiple keyboards such as an upper keyboard, a lower keyboard, a pedal keyboard, and a solo keyboard, and each keyboard can produce multiple series of performance sounds with different musical characteristics such as timbre and range. It is composed of By the way, when adding reverberant sound to the performance sound of each keyboard (each series) in such an electronic musical instrument, depending on the manner of selecting the tone of each keyboard, there are tones that are suitable for adding reverberant sound and tones that are not suitable for adding reverberant sound. may be selected at the same time. For example, if a vibrafon tone is selected in the upper keyboard or solo keyboard, and an organ tone is selected in the lower keyboard, the vibrafon tone has a long amplitude envelope and is amplitude modulated, so reverberation is added. This is not necessary; on the other hand, an excellent effect can be obtained by adding a long and deep reverberant sound, such as the sound of a performance in a church, to the tone of an organ. Furthermore, depending on the performance situation, in order to achieve an effect of pushing a certain tone to the forefront, it may be desired to produce only the sound played on the keyboard of that tone without adding reverberation. In this way, when adding reverberation to the performance sounds of each series in an electronic musical instrument that has multiple musical tone series,
There is a need for a configuration in which a series to which reverberant sound is to be added can be freely selected depending on the selected timbre of the keyboard and the performance situation. The present invention has been made in view of the above-mentioned requirements, and its object is to provide an electronic musical instrument that allows a user to arbitrarily select a series to which reverberation is to be added from among a plurality of musical tones. By the way, when adding reverberation sound using an electronic circuit, BBD (Bucket Brigade Device) and
Some use analog delay elements such as CCDs (Charge Coupled Devices). However, in devices using such analog delay elements, the longer the reverberation time is increased, that is, the more the number of series-connected analog delay elements is increased, the lower the output signal level and the more noticeable the decline in the S/N ratio becomes. However, the drawback was that natural reverberation could not be obtained. Another drawback is that once the reverberation characteristics, including the reverberation time, are set, they cannot be easily changed thereafter. Therefore, in this invention, in order to prevent the S/N from decreasing even if the reverberation time is increased and to make it possible to easily change the reverberation time, multiple series of digital musical sound signals with different musical sound characteristics such as timbre are generated. digital musical sound signal generating means for adding reverberation to an input digital musical sound signal and outputting the resultant digital musical sound signal; a selection means for selectively supplying the reverberation sound to the sound addition means; the reverberation sound addition means includes: a reverberation sound indication means for selectively instructing reverberation characteristics of the reverberation sound from among a plurality of reverberation characteristics; a control program memory that stores a plurality of control programs for forming reverberant sound corresponding to each of the reverberation characteristics that can be specified, and outputs a control program that corresponds to the reverberation characteristics specified by the reverberation characteristics instruction means; A reverberation sound forming means including a calculation means 40 and a data memory 190 having a plurality of addresses, and a control program memory 300 that stores parameters regarding delay time and calculation coefficients corresponding to the reverberation characteristics instructed by the reverberation characteristics instruction means. a parameter generation means 20 that generates data according to the output of the control program memory 300, and a parameter generating means 20 that writes and reads data to and from the data memory 190 based on the output of the control program memory 300 and the parameters related to the delay time;
The reverberation sound forming means includes a control means 303 for outputting a memory control signal for address designation as well as an arithmetic control signal for the arithmetic means 40 based on the output of the control program memory 300; By performing a predetermined operation on the signal read out from the data memory 190 in accordance with the control signal, the calculation coefficient, and the digital musical tone signal, the reverberation characteristics instruction means specifies the reverberation characteristic instruction for the digital musical tone signal. It is designed to output with reverberation characteristics added. Hereinafter, this invention will be explained in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of an electronic musical instrument according to the present invention, in which an upper keyboard 1, a lower keyboard 2,
Pedal keyboard 3, key depression detection circuit 4, sound generation assignment circuit 5, musical tone signal generation circuit 6, tone setting circuit 7, musical tone data accumulator 8, musical tone data selection circuit 9, reverberation sound addition keyboard selection circuit 10, reverberation sound addition It consists of a device 11, DA converters 12 and 13, and sound systems 14 and 15. The upper keyboard 1, lower keyboard 2, and pedal keyboard 3 each have a plurality of keys and a plurality of key switches that operate when each key is pressed, and the operation of each key switch is determined by a key press detection circuit 4. detected. The pressed key detection circuit 4 detects the operation of each key switch on the upper keyboard 1, lower keyboard 2, and pedal keyboard 3, and generates and outputs a key code KC representing the pressed key. In this case, the key code KC is composed of a keyboard code KBC representing the type of keyboard, an octave code OC representing the range of the key, and a note code NC representing the timbre.
is supplied to the sound generation allocation circuit 5. The sound generation assignment circuit 5 assigns a key code supplied from the key press detection circuit 4 to one of the plurality of time-division sound generation channels in the musical tone signal generation circuit 6.
Assign the pronunciation of the musical tone corresponding to the pressed key indicated by KC,
The key code KC of the pressed key is time-divisionally output at the channel timing corresponding to the assigned time-division sounding channel. It is assumed here that 12 time-division sounding channels are provided. In this case, the pronunciation assignment circuit 5 uses the key code
A musical tone signal generation circuit 6 outputs a key-on signal KON that controls the sound generation of musical tones assigned to each sound generation channel in synchronization with the time-division output timing of the KC.
supply to. As mentioned above, the musical tone signal generation circuit 6 has, for example, 12 time-division sound generation channels, and when the key code KC of the pressed key is supplied from the sound generation allocation circuit 5 in synchronization with the timing of each channel, this key code KC Based on the timbre information TSD set by the timbre setting circuit 7, musical tone data GD (digital musical tone signal ) is formed for each sound channel and outputted in a time-division manner. This musical tone signal generation circuit 6 generates musical tone data GD using musical tone signal forming methods such as a waveform memory read method, a harmonic synthesis method, a frequency modulation method, and an amplitude modulation method. In addition, the musical tone data GD of each pronunciation channel
is given an amplitude envelope from attack to decay by the key-on signal KON of its own channel. In this case, the timbre setting circuit 7 is capable of setting timbres for each of the upper keyboard 1, lower keyboard 2, and pedal keyboard 3, and outputs timbre information TSD corresponding to each keyboard. and,
In each sound channel in the musical tone signal generation circuit 6, the keyboard code KBC of the own channel is
The musical tone data GD of the tone corresponding to the tone color information TSD regarding the keyboard indicated by is formed. This allows multiple series of musical tone data GD with different tones for each keyboard.
is formed. In this manner, the musical tone signal generation circuit 6 forms and outputs musical tone data GD regarding the pressed keys assigned to each sound generation channel in a time-division manner, and supplies the generated musical tone data to the musical tone data accumulator 8. The musical tone data accumulator 8 synthesizes the musical tone data GD formed by each sound generation channel of the musical tone signal generation circuit 6 for all channels and outputs it as synthesized musical tone data ΣGD of musical tones corresponding to the pressed keys of all the keys. Further, for each keyboard, musical tone data related to the pressed keys of the keyboard are synthesized and output as musical tone data ΣGD _U , ΣGD _L , ΣGD _P for each keyboard. In this case, the tone data GD formed in each tone generation channel is distributed to each keyboard by the tone generation assignment circuit 5.
This is done using the keyboard code KBC supplied by . Note that ΣGD _U , ΣGD _L and ΣGD _P represent upper keyboard musical tone data, lower keyboard musical tone data and pedal keyboard musical tone data, respectively. The synthesized musical tone data ΣGD related to all the pressed keys of the keyboard synthesized by the musical tone data accumulator 8 is converted into an analog musical tone signal by the DA converter 13 and outputted from the sound system 15 as a musical tone. On the other hand, musical tone data ΣGD _U , ΣGD _L ,
ΣGD _P is supplied to the musical tone data selection circuit 9, where it is selected according to the keyboard selection information KBS from the reverberation sound addition keyboard selection circuit 10, and is supplied to the digital reverberation sound addition device 11. Then, the reverberation sound adding device 11 selects and supplies musical tone data ΣGD _U from the musical tone data selection circuit 9,
Reverberation sound having a desired reverberation characteristic is added to ΣGD _L and ΣGD _P and then supplied to the DA converter 12 . As a result, musical sound data (ΣGD _U ,
(either ΣGD _L or ΣGD _P ) is converted into an analog signal by the DA converter 12, and then produced by the sound system 14 as a musical tone with added reverberation. FIG. 2 is a circuit diagram showing an example of a specific configuration of the musical tone data accumulator 8, in which the synthesized musical tone data ΣGD is stored in a circuit consisting of an adder 8A, a register (delay flip-flop) 8B, a latch 8C, and an AND gate 8D. It is formed as a result. That is, the tone data GD formed by each sound generation channel is supplied to the addition input A of the adder 8A. The adder 8A is connected to the first to twelfth sounding channels.
Store the musical sound data GD of the pronunciation channel in register 8.
The output value of the register 8B is supplied to the addition input B via the AND gate 8D only when the timing signal ₁ is "1". As shown in the time chart of FIG. 3, timing signal ₁ is a timing signal that becomes "1" at the channel timing corresponding to the first sound generation channel among the 12 channel timings defined by clock pulse φ _A. This timing signal 1 is an inverted signal (Fig. 3 e) of T ₁ (Fig. 3 d), and this timing signal ₁ is supplied to the AND gate 8D as a gate control signal. Therefore, the output value of the register 8B is continuously inputted to the addition input B of the adder 8A at channel timings other than the channel timing corresponding to the first sound generation channel. Therefore, the adder 8A is
The musical tone data GD of the first sound generation channel is output as is and supplied to the register 8D. Then, the register 8B outputs the musical tone data GD of the first sound generation channel to the clock pulse φ _A shown in FIG. 3a.
It is taken in at the timing of occurrence of clock pulse _φB and outputted at the timing of occurrence of clock pulse φB shown in FIG. 3b. That is, the register 8B outputs input data with a time delay corresponding to one channel timing.
Then, when the timing signal ₁ becomes "1" at the channel timing corresponding to the second sound generation channel, the AND gate 8D becomes open, so that the tone data of the first sound generation channel held in the register 8B is GD is input to addition input B of adder 8A via this AND gate 8D. At this time, the addition input A of the adder 8A has the second
Since the tone data GD of the first and second tone generation channels is input, the adder 8A outputs the sum of the tone data of the first and second tone generation channels. This added value is held in register 8B. By repeating this operation until the channel timing corresponding to the 12th sound channel, the
At the end of the 12 channel timings, the total addition value ΣGD of the musical tone data GD of the 12 sounding channels is obtained. This total addition value ΣGD is determined by the latch 8 at the rising edge of the timing signal _T1 .
C, and while the channel timing goes through this latch 8C (until the next signal _T1 rises)
The signal is held and output from the output of the latch 8C as synthesized musical tone data ΣGD. Fig. 3 f shows synthesized musical tone data ΣGD(t) and ΣGD(t
+1). On the other hand, musical tone data ΣGD _U , ΣGD _L ,
ΣGD _P is also formed by a similar circuit. However, since the adder 8E, which adds new musical tone data and already accumulated musical tone data, is shared by the accumulation circuit series for each keyboard, the input stage of the addition input B of the adder 8E is A selector 8J is provided at the input stage of registers 8G, 8L, and 8Q that hold each total value of musical tone data for each keyboard.
8K and 8P are provided respectively. The circuit consisting of adder 8E, selectors 8J, 8F, register 8G, latch 8H and AND gate 8I constitutes an accumulation circuit series that forms upper keyboard musical tone data ΣGD _U , and adder 8E, selector 8J , 8K, register 8L, latch 8M, and AND gate 8N constitute an accumulator circuit series for forming lower keyboard tone data ΣGD _L. Further, an adder 8E, selectors 8J, 8
The circuit consisting of P, register 8Q, latch 8R, and AND gate 8S constitutes an accumulation circuit series for forming pedal keyboard musical tone data ΣGD _P. First, the musical tone data GD of the first pronunciation channel
is added, this musical tone data GD is sent to adder 8
is fed to the addition input A of E. At this time, the AND gates 8I, 8N, and 8S of each accumulator circuit series are all closed by the timing signal ₁ , so the three selection inputs A, B, and C of the selector 8J are
are all "0", and the input value of the addition input B of the adder 8E is "0". Therefore, the adder 8E outputs the musical tone data GD supplied to the addition input A as is, and selectors 8F and 8 of each accumulation circuit series
Commonly supplied to selection input A of K and 8P. The selectors 8F, 8K, and 8P select and extract the musical tone data GD output from the adder 8E for each keyboard. In other words, 8F is the keyboard code
When the upper keyboard signal UC indicating the upper keyboard 1 obtained by decoding KBC by the decoder T8 is "1", the musical tone data input from the adder 8E to the selection input A
GD selects this musical tone data GD as relating to the pressed key of the upper keyboard 1 and supplies it to the register 8G. Further, when the lower keyboard signal LC indicating the lower keyboard 2 obtained by decoding the keyboard code KBC by the decoder 8T is "1", the selector 8K selects the tone data GD input from the adder 8E to the selection input A to the lower keyboard 2. This musical tone data GD is selected as data relating to the pressed key and is supplied to the register 8L. Further, when the pedal keyboard signal PC indicating the pedal keyboard 3 obtained by decoding the keyboard code KBC by the decoder 8T is "1", the selector 8P selects the musical tone data GD input from the adder 8E to the selection input A to the pedal keyboard 3. This musical tone data GD is selected as relating to the pressed key and is supplied to the register 8Q. Therefore, the musical tone data output from the adder 8E
GD is a cumulative circuit series register 8G, 8L, 8 provided corresponding to each keyboard 1, 2, 3.
It is distributed and supplied to Q respectively. Here, if the musical tone data GD of the first sound generation channel is related to the press board of the pedal keyboard 3, this musical tone data GD is passed through the selector 8P to the register 8Q.
and is held in this register 8Q. Next, when the timing signal ₁ becomes "1" at the channel timing corresponding to the second sound generation channel, the AND gates 8I, 8N, 8S of each accumulation circuit series are opened. Therefore, the values held in the registers 8G, 8L, 8Q of each accumulation circuit series are the same as those of the open AND gates 8I, 8.
Selectors 8F, 8 of own series via N, 8S
It is fed back to the selection inputs B of the selectors K and 8P, and is also supplied to the selection inputs A, B and C of the selector 8J, respectively. The selector 8J selectively outputs the musical tone data GD related to the upper keyboard 1 supplied to the selection input A via the AND gate 8I when the upper keyboard signal UC is "1", and when the lower keyboard signal LC is "1". At times, the musical tone data GD related to the lower keyboard 2, which is supplied to the selection input B via the AND gate 8N, is selectively outputted, and furthermore, when the pedal keyboard signal PC is "1", the musical tone data GD is supplied to the selection input C via the AND gate 8S. Musical sound data related to pedal keyboard 3
GD is selectively output, and this selective output is supplied to the addition input B of the adder 8E. Therefore, the musical tone data of the second sounding channel
When GD is related to the pressed key of the upper keyboard 1, the musical tone data GD held in the register 8G is supplied to the addition input B of the adder 8E, and the musical tone data GD held in the register 8G is supplied to the addition input A. Musical tone data GD of the pronunciation channel is supplied. However, in this example, the first sound channel is pedal keyboard 3.
Since the tone data GD is not yet stored in the register 8G, the adder 8E outputs the tone data GD of the second tone generation channel regarding the upper keyboard 1 as is. and,
This musical tone data GD is held in the register 8G via the selector 8F. Next, the musical tone data GD of the third pronunciation channel
is also related to upper keyboard 1, register 8
Since the tone data GD of the second tone generation channel related to the upper keyboard 1 is already stored in G, the adder 8E outputs the sum value of the tone data GD of both the second tone generation channel and the third tone generation channel. do. The added value of these two tone data GD is supplied to the register 8G via the selector 8F and held in this register 8G. in this case,
The data in the registers 8L and 8Q of the cumulative circuit series related to the lower keyboard 2 and pedal keyboard 3 is held by inputting the outputs of the registers 8L and 8Q to their own inputs via the AND gates 8N and 8S and the selection inputs B of the selectors 8K and 8P, respectively. This is done by returning to Japan. By performing this operation in the same way for each musical tone data GD of the 12 musical tone channels, registers 8G, 8L, and 8Q contain the musical tone data GD for each keyboard in the channel where the timing of each channel has completed one cycle. The total values ΣGD _U , ΣGD _L and ΣGD _P are stored. The musical tone data ΣGD _U , ΣGD _L and ΣGD _P for each keyboard obtained in this way are used for latches 8H, 8M.
and 8R, respectively, to the tone data selection circuit 9 of FIG. Then, the musical tone data selection circuit 9 selects musical tone data ΣGD _U , ΣGD _L , ΣGD _P related to a predetermined keyboard and supplies them to the reverberation sound adding device 10 . Figure 4 shows the musical sound data of the keyboard to which reverberation should be added.
This is a circuit diagram showing a specific example of the musical tone data accumulator 8 in the case of accumulating only GD, and is an accumulation that forms synthesized musical tone data ΣGD of musical tone data GD regarding the pressed keys of all keys 1, 2, and 3. The circuit series is constructed in the same manner as in FIG. On the other hand, only one accumulation circuit series is provided to form synthesized musical tone data for each keyboard, and the keyboard selection switches SW _U , SW _L ,
The configuration is such that only the musical tone data GD of the keyboard specified by SW _P is selected by the selector 8V and accumulated. In other words, selection input A of selector 8V
is supplied with the added value of the adder 8U, and the selection input B
The output value of register 8W is converted to
The selection control input SA receives an upper keyboard signal UC, a lower keyboard signal LC, and a pedal keyboard signal PC in response to the closing of switches SW _U , SW _L , and SW _P via an OR gate 8Z.
Either one is selectively supplied. Therefore, the selector 8V selects the added value of the adder 8U and supplies it to the register 8W only at the timing of the tone generation channel for the keyboard specified by closing the switches SW _U , SW _L , SW _P . By this,
From the latch 8X, synthesized musical tone data relating to the depressed keys of the keyboard (one or more) selected by the switches SW _U , SW _L , SW _P are obtained. By the way, the musical tone signal generation circuit 6 generates musical tone data GD of each sound channel at a high sampling frequency.
However, in the reverberation sound addition device 11, it is not necessary to form reverberation sound at the same sampling frequency as that for forming musical sound data GD. For example, when forming musical sound data GD at a sampling frequency of 50 KHz, A sampling frequency of about 25KHz is sufficient to form the reverberant sound. Therefore, as shown in FIG. 5, a sampling rate conversion circuit 16 is provided between the musical tone data selection circuit 9 and the reverberation sound adding device 11, and the synthesized musical tone data ΣGD _U , ΣGD for each key selected by the circuit 9 is provided. _L ,
The sampling rate of ΣGD _P may be lowered. i.e. 50KHz timing signal
The frequency of T ₁ is divided by 1/2 by the frequency dividing circuit 16A to obtain a 25KHz sampling pulse Ts, and the musical tone data that has passed through the digital filter 16B is sampled and held by the latch 16C using this sampling pulse Ts, and this sample and hold output is used for reverberation. The sound is supplied to the sound adding device 11. By doing so, it is possible to reduce the memory capacity when forming reverberant sound in the reverberant sound adding device 11. Note that the digital filter 16B is for removing aliasing noise components when converting the sampling rate, and may be unnecessary depending on the frequency band of the musical tone signal. Figure 6 shows a reverberation sound adding device 11 used in this invention.
A block diagram showing one embodiment; FIG. 7 is a functional block diagram functionally representing the configuration of this embodiment; FIGS. 8 and 9 show how digital memory is used to generate reverberation sound with a desired delay time. FIG. 2 is a block diagram showing the basic configuration of a delay circuit for making a delay circuit. For convenience of explanation, we will first explain the basic configuration and operation of the delay circuit shown in FIGS. 8 and 9,
Next, the process of forming reverberant sound will be explained with reference to the functional block diagram of FIG. 7, and then the specific structure and operation of the embodiment shown in FIG. 6 will be explained. Basic configuration of a delay circuit using a digital memory When musical tone data GD(t) of an input musical tone signal sampled sequentially at a predetermined sampling period _T0 is sequentially stored in a digital memory as time elapses, the time ( In order to read the musical tone data GD(t-i) stored at time t-i) at time t after i time has elapsed, the address information ADR(t) when the sampling time is t must be changed during i time. Add or subtract the address interval ΔADR as shown in the following equation (1) or (2), and calculate the time (t
-i), and provide this address information ADR(t-i) to the address input of the digital memory. ADR (t-i) = ADR (t) + ΔADR ... (1) ADR (t-i) = ADR (t) - ΔADR ... (2) This allows the memory to be stored at time (t-i). Musical tone data GD(t-i) can be read out with a delay of i time expressed as i=ΔADR×T ₀ (3).
That is, if the address interval ΔADR corresponding to the desired delay time i is given as delay time information, musical tone data GD(t-
i) can be read with a delay of i time. In this case, to obtain the address information ADR(t-i) at time (t-i) using equation (1) above, the musical tone data GD(t) is transferred from a high-order address to a low-order address as time passes. This is applied when the ranking is memorized. Furthermore, equation (2) is applied when musical tone data GD(t) is stored sequentially from a low address to a high address. Therefore, the delay time is the difference between the digital memory DM that sequentially stores the musical tone data GD(t) and the above (1).
An address information generation circuit AG that forms read address information ADR (t-i) shown by the equation or equation (2), and a delay length data memory DDM that generates the address interval ΔADR as delay time information DLD. Basically provided. FIG. 8 is a block diagram showing an example of a delay circuit based on this concept, which includes a digital memory DM, an address information generation circuit AG, a delay length data memory DDM, and a multiplier M. As shown in the time chart of FIG. 10, the digital memory DM stores the musical tone data GD(t) sampled at a predetermined period _T0 in accordance with the sampling pulse _Ts to each high-order address from "0" to "9". It is stored in order from the "9" side toward the lower address "0", and is configured by, for example, a RAM (random access memory) or a shift register. Musical sound data in this digital memory DM
Designation of the write address and read address of GD(t) is performed by address information generation circuit AG. In other words, the address information generation circuit
AG includes an address counter AC and an adder AD, and the write address information ADR(t) and ADR(t+
1), ADR(t+2), . Output as DM/ADR. i.e. address counter AC
counts (down counts) the sampling pulse Ts with period T ₀ , and calculates the count value as musical tone data GD(t) at the current sampling time t.
output as write address information ADR(t),
This information ADR(t) is supplied to the adder AD. On the other hand, the delay length data memory DDM stores time information DLD (ΔADR=
i/T ₀ ) to the other addition input of the adder AD. Then, at the sampling time t, the adder AD first performs the calculation expressed by the above-mentioned equation (1), and uses the calculated value as the musical tone data GD of i time before.
(t-i) read address information ADR(t-i)
Then, the output information ADR (t) of the address counter AC is directly used as the write address information ADR of the musical tone data GD (t) at the current time t.
Output as (t). As a result, from the digital memory DM,
At time t, musical tone data GD(t-i) stored at time i hours ago (t-i) is read out, and musical tone data GD(t) at current time t is read out.
is stored at the address specified by address information ADR(t). The musical tone data GD(t-i) read out from the digital memory DM with a delay of i time in this way is
The signal is multiplied by a coefficient K for amplitude level control in a multiplier M and output after level control. Such operations are performed at each sampling time.
As a result, it is possible to generate reverberant sound delayed by i hours from the input musical tone. In this case, multiple pieces of delay time information that differ at one sampling time
If DLD is applied sequentially in a time-sharing manner, information regarding multiple reverberant sounds with different delay times can be extracted within the same sampling time. Therefore, the delay circuit shown in Figure 8 is used to form early reflected sounds with complex reverberation characteristics that randomly vary in amplitude level and delay time depending on the distance to the surrounding wall or other reflecting body. be done. FIG. 9 is a block diagram showing another example of the delay circuit, in which the address counter AC of the address information generation circuit AG is constructed with a preset type down counter. Then, by presetting delay time information DLD corresponding to a desired delay time i for address counter AC and performing a down-count operation from this preset value (DLD), address information ADR (t ), ADR(t+1),...
The repetition period of ADR (t+i) is delay time information
The musical tone data GD(t) at the current time t is set to match the delay time specified by DLD.
The tone data GD(t-i) stored i hours ago is read from the address at which it is to be stored. In other words, when the digital memory DM consists of 10 words as shown in Figure 9, the maximum value of the address interval is " ₁₀ ", so the musical tone data GD (t- 10), it is possible to read out the desired delay time i, for example, 6·T ₀
In this case, the output information of address counter AC
DM/ADR 5, 4, 3, 2, 1, 0, 5,...
... 0 is repeated, and the address range used in the digital memory DM is set to the desired delay time i.
(i=6・T ₀ ), and the address to which the musical tone data GD(t) sampled at the current time t is to be written is changed to the musical tone data GD(t−i ) to match the written address, and the musical tone data GD at the current time t.
(t) is written i hours before the address to be written, and musical tone data GD(t-i) is read out. For this reason, in the delay circuit of FIG. 9, the output information DM of the address counter AC is
A maximum value detection circuit MXD is provided which detects that ADR changes from "0" to "9" and presets the time information DLD output from the delay length data memory DDM into the address counter AC based on this detection signal. There is. On the other hand, the delay circuit in FIG. 9 does not directly write the musical tone data GD(t) sampled at the current time t into the digital memory DM, but returns the musical tone data GD(t-i) from i hours ago at a predetermined rate. Then, the feedback value K・GD(t−i) and the musical tone data GD sampled at the current time t
(t) is written.
For this purpose, a coefficient K
A multiplier M multiplies the multiplier M and returns it to the data input side of the digital memory DM, and the output data K・GD(t−i) of the multiplier M and the musical tone data GD at the current time t.
(t) and the added value “GD(t)+K・
An adder AD is provided which supplies "GD(t-i)" to the data input of the digital memory DM. Therefore, in the delay circuit configured in this way, when the desired delay time i is 6·T ₀ ,
When the output information DA/ADR of the counter AC changes from "0" to the maximum value ("9" in this example), the delay time information DLD expressed as DLD=6-1=5 is stored in the address counter AC. Preset. As a result, the address counter AC changes to 5, 4, 3, 2, 1, 0, 5, . . . (every sampling period T ₀ ) as the sampling time progresses.
Address information that changes from 0 to DM・
ADR will be output repeatedly. and,
At each sampling time, address information
Musical tone data GD(t-i) from i hours ago stored at the address specified by DM/ADR is first read out, and then musical tone data GD(t-i) from i hours ago is read from the same address as this read address. i)
and the musical sound data GD sampled at the current time t.
(t) and added at a predetermined ratio, the data “GD
(t)+K·GD(t−i)” is written. Therefore, in the delay circuit configured in this way, musical tone data GD at the current sampling time t
(t) write address and musical tone data i hours ago
Since the read address of GD(t-i) is the same and the musical sound data GD(t-i) from i hours ago is fed back, data related to reverberant sound whose amplitude level and delay time regularly change can be collected. It can be taken out. Therefore, the delay circuit shown in FIG. 9 is used to generate reverberant sound with regular reverberation characteristics. Furthermore, when the musical tone data is multiplied by the coefficient K,
The level of the final reverberant sound data will be higher than the original musical sound data, so
In reality, data regarding this reverberant sound is led to the reverberant sound output section through an attenuator. In this case, if the coefficient K is set to "-1<K<0", an attenuator is not required. Next, the process of forming reverberant sound will be explained using the functional block diagram shown in FIG. Process of Forming Reverberant Sound First, the process of forming reverberant sound in the embodiment shown in FIG. The process of forming reverberant sound in which the delay time changes regularly. Here, these early reflected sounds and reverberant sounds are formed by mutually independent delay circuit series. In FIG. 7, musical tone data GD(t) sampled at a predetermined period T ₀ is supplied to an early reflected sound forming section 1000, which is a first delay circuit series. The early reflected sound forming section 1000 utilizes the delay circuit shown in FIG. 10 types of musical tone data GD (t-i ₁ ), GD (t-i ₂ ), ... from i _o time (n = 1 to 10) ago
Multipliers M1 to M that multiply GD (ti ₁₀ ) by an arbitrary amplitude level control coefficient K _o (n=1 to 10)
10 and the multiplication value outputs of these multipliers M1 to M10.
K ₁・GD (t-i ₁ ), K ₂・GD (t-i ₂ ), ...K ₁₀・
Find the sum of GD (t-i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o・GD (t-i _o ),
The adder SUM1 outputs the sum ₁₀ 〓 ⁿ⁼¹ K _o ·GD (t-i _o ) as the instantaneous value ECH (t) of the early reflected sound at the current time t. Note that the adder SUM1 calculates the above sum ₁₀ 〓 ⁿ⁼¹ K _o・GD
It has a built-in register R0 that temporarily stores (t- _io ) until the next sampling time (t+1). In the early reflected sound forming section 1000 having such a configuration, the musical tone data GD(t) sampled at the current time t is written to the address corresponding to the current time t among the 2048 word storage addresses of the memory D0. Next, register R in adder SUM1
Since the total sum ₁₀ 〓 ⁿ⁼¹ K _o ·GD (t-1 - i _o ) at the previous sampling time (t-1) is stored in register R0, the contents of this register R0 are reset. Next, 10 types of _musical tone data GD (t
-i ₁ ) to GD (t-i ₁₀ ), in order to read musical tone data G (t-i ₁ ) with delay time i ₁ from memory D0,
An address in the memory D0 corresponding to the delay time _i1 is specified, and musical tone data GD (t- _i1 ) sampled _i1 hours ago is read from the address. In this case, the address for reading out the musical tone data GD (t-i ₁ ) i ₁ hour ago is determined by the above-mentioned equation (1). The musical tone data GD (t-i ₁ ) read out in this way and having a delay time i ₁ is input to a multiplier M1, and the multiplier M1 outputs the first reflected sound having a delay time i ₁ .
Multiplied by coefficient K ₁ for amplitude level control corresponding to ECH ₁ . Then, the multiplication value K ₁・GD (t−i ₁ )
is input to the adder SUM1 and added to the current value of register R0, and the added value is stored again in register R0. In this case, the contents of the register R0 are reset immediately after writing the musical tone data GD(t) at the current time t, so the contents written to the register R0 at this time are the data _K1 ·GD(t-
i ₁ ). In this way, musical tone data GD with delay time i ₁
When the readout process and level control process for (t-i ₁ ) are completed, that is, when the process regarding the first reflected sound ECH ₁ is completed, the second reflected sound with delay time i ₂ is
The reading process and level control process of the musical tone data GD(t-i ₂ ) regarding ECH ₂ are performed in the same manner as the process of forming the first reflected sound ECH ₁ . As a result, the first reflected sound is stored in register R0 in adder SUM1.
The sum of the data _{K 1 ·} GD (t-i ₁ ) regarding ECH 1 and the data K ₂ · GD (t-i ₂ ) regarding the second reflected sound ECH ₂ is "K ₁ · GD (t-i ₁ ) + K ₂・GD(t−i ₂ )” is stored. Such processing is similarly performed for the third reflected sound _ECH3 to the tenth reflected sound _ECH10 . As a result, musical tone data _K1 ·GD(t- _i1 ) regarding the first reflected sound _ECH1 to the tenth reflected sound _ECH10 are stored in the register R0.
~ Total sum of K ₁₀・GD (t−i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o・GD (t−i _o )
is memorized. And this total sum ₁₀ 〓 ⁿ⁼¹ K _o・GD(t
-i _o ) is outputted via the switch circuit SW as the instantaneous value ECH(t) of the early reflected sound consisting of the first reflected sound ECH ₁ to the tenth reflected sound ECH ₁₀ . As shown in Table 1 below, the switch circuit SW selects and outputs the output of the register R0 at the initial reflected sound formation processing time Ta within one sampling period _T0 , _Tb
In this case, the output of the second delay circuit series is selectively output.

[Table] The data ECH(t) selectively output by this switch circuit SW is converted into an analog signal by the DA converter 12 in FIG. pronounced as Therefore, the first reflected sound ECH ₁ to the 10th reflected sound ECH ₁₀
By varying the delay time i _o and the coefficient K _o for amplitude level control, it is possible to obtain an early reflected sound whose amplitude level and delay time vary randomly, as shown in FIG. Here, the sampling period T ₀ of the input musical tone is 0.04
ms (25KHz), if musical tone data GD (t-1626) stored at an address 1626 words away from the write address ADR (t) of musical tone data GD (t) at current time t is read, The delay time i is i=1626×0.04≒65ms, and the early reflection sound is delayed by about 65ms from the input musical tone.
Can generate ECH _o . On the other hand, the musical tone data GD(t) obtained by sampling the input musical tone at a predetermined period T ₀ is also supplied to the second delay circuit series that forms the reverberant sound after the initial reflected sound is generated. This second delay circuit series is connected to the musical tone data GD.
(t) is delayed by j hours to create a bandpass filter BPF.
a delay memory D10 supplied to
A digital band-pass filter BPF consisting of a low-pass filter LPF and a high-pass filter HPF that pass only a predetermined frequency band component of GD (t-j); and the band-pass filter BPF.
A first reverberation sound forming section 2000 having a comb-type filter configuration forms reverberation sound data RVD ¹ with a coarse delay time interval based on the musical sound data GD (t-j) that has passed through the
and a second reverberant sound forming section 3000 having an all-pass filter configuration that forms reverberant sound data RVD ² with dense delay time intervals based on the reverberant sound data RVD ¹ . In such a configuration, the musical tone data GD(t) at the current time t is written to the address ADR(t) corresponding to the current time t among the 2048 word storage addresses in the memory D10. Next, memory D1
In order to read the data GD (t-j) of j hours ago from among the musical tone data GD (t) stored in 0, the address of the memory D10 corresponding to the delay time j is specified, and the data j hours ago from the address is specified. Sampled musical tone data GD (t-j) is read out. In this case, the address for reading out the musical tone data GD (t-j) of j hours ago is determined by the above-mentioned equation (1), as in the case of forming the early reflected sound.
And the delay time j here is the 10th reflected sound ECH ₁₀
The delay time for i is slightly larger than ₁₀ (j>i ₁₀ )
It is set. The musical tone data GD(t-j) with a delay time j thus read out from the memory D10 is input to the multiplier M11 of the low-pass filter LPF, where it is multiplied by a predetermined coefficient _K11 . and,
The multiplied value _K11 ·GD(tj) is temporarily stored in register R1. Next, from memory SD0 having a storage address of one word, one sampling time (1.
T ₀ ) Previously written musical tone data GD (t-j-1)
is read out, and this data GD(t-j-1) is multiplied by a predetermined coefficient _K12 in a multiplier M12. Next, the multiplication value output of multiplier M12 K ₁₂・GD
(t-j-1) and musical tone data _K11・GD(t-j) from j hours ago temporarily stored in register R1, and the added value “ _K12・GD(t-j-
1) +K ₁₁ ·GD(t-j)'' is temporarily stored in register R1 and also temporarily stored in register R2. Next, musical tone data GD ( _t
-j-1) is read out again from memory SD0, and this data GD(t-j-1) is multiplied by a predetermined coefficient _K13 in multiplier M13. Then, this multiplication value K ₁₃ · GD (t-j-1) is the value "K ₁₂ · GD (t-j-1) +
K ₁₁・GD(t−j)” and the added value K ₁₂・GD(t−j−1) +K ₁₁・GD(t−j) +K ₁₃・GD(t−j−1) is stored in the register. It is temporarily stored again in R2. Next, the value “K ₁₂・GD” temporarily stored in register R1 is
(t-j-1)+K ₁₁・GD(t-j)" is used in the next sampling period (t+1), so this value "K ₁₂・GD(t-j-1)+K ₁₁・GD(t -j)” is written to the memory SD0. By performing such an operation every sampling period _T0 , the low pass filter LPF
The register R2 outputs musical tone data GD (t-j) of j hours ago from which high frequency components in a predetermined band have been removed, and this musical tone data GD (t-j) is sent to a high-pass filter HPF. Then, the high-pass filter HPF removes low frequency components in a predetermined band from the musical tone data GD (t-j) of j hours ago in the same way as the low-pass filter LPF. That is, the output data GD (t-j) of the register R2 of the low-pass filter LPF is input to the multiplier M14.
is inputted into the multiplier M14 and multiplied by a predetermined coefficient _K14 . Then, the multiplication value K ₁₄・
GD(t-j) is temporarily stored in register R3.
Next, memory SD1 has a storage address of one word.
The musical tone data GD (t-j-1) written before the sampling time (1·T ₀ ) is read out from , and a predetermined coefficient K ₁₅ is added to this data GD (t-j-1) in the multiplier M15. Multiplyed. Next, the multiplier M
Multiply value K ₁₅・GD (t-j-1) obtained from 15
is added to the musical tone data K ₁₄ · GD (t-j) from j hours ago, which is temporarily stored in register R3, and the added value is "K ₁₄ · GD (t-j) + K ₁₅ · GD (t-j-
1)” is temporarily stored in register R3, and
It is also temporarily stored in register R4. Next, the data GD (t-j-1) written one sampling time (1・T ₀ ) before the current time t is stored in the memory SD1.
This read data GD(t-
j-1) by a predetermined coefficient _K16 in a multiplier M16. Then, this multiplication value K ₁₆・GD(t
-j-1) is the value temporarily stored in register R4 "K ₁₄・GD (t-j) + K ₁₅・GD (t-j-1)"
The added value _K16.GD (t-j-1)+ _K14.GD (t-j)+ _K15.GD (t-j-1) is temporarily stored in register R4. Next, the value “ _K14・GD(t−
j)+K ₁₅・GD(t-j-1)" is used in the next sampling period (t+1), so this value "K ₁₄・GD(t-j)+K ₁₅・GD(t-j-1) " is written to memory SD1. By performing such an operation every sampling period _T0 , the register R4 of the high-pass filter HPF outputs musical tone data GD (t-j) of j hours ago from which low frequency components in a predetermined band have been removed. Note that register R1 of the low-pass filter LPF
After writing the contents of the register to memory SD0, it is not used until the next sampling period, so
It can be shared with register R3 of high pass filter HPF. In this way, the bandpass filter BPF removes the low frequency components and high frequency components of a predetermined band from musical tone data GD(t-j) j hours ago.
is input to the first reverberant sound forming section 2000. The first reverberation sound forming section 2000 includes delay circuits 2000A and 20 having comb-type filter configurations having different delay times.
00B and 2000C are provided in parallel. 3
delay circuits 2000A, 2000B, 2000
The reason why C is provided in parallel is to flatten the frequency characteristics of a delay circuit with a comb-type filter configuration, which would be wavy as shown by symbols A, B, and C in Figure 12 if it were used alone. It's for a reason. In other words, three delay circuits 2000A and 2000 with different delay times
By providing 00B and 2000C in parallel,
The overall frequency characteristic can be flattened as shown by symbol D in FIG. In this case, the degree of flattening improves as the number of parallel connection of delay circuits increases. In this embodiment, the delay time of delay circuit 2000A is set to be the longest, followed by the longest delay time of delay circuit 2000B, and the delay time of delay circuit 2000C is set to be the shortest. And each delay circuit 200
0A, 2000B, and 2000C have the same configuration except for the delay time settings. Therefore, in the figure, circuits 2000B and 20
Regarding 00C, only the numbers of multipliers, registers, and memories are shown, and only the delay circuit 2000A is shown in detail. In the first reverberation sound forming section 2000 having such a configuration, the j that has passed through the bandpass filter BPF is
The previous musical tone data GD (t-j) is first given a coefficient K ₁₇ for amplitude level control in the multiplier M17.
is multiplied. Then, the multiplication value K ₁₇・GD(t
-j) is temporarily stored in register R5 in multiplier M17. Next, musical tone data written x ₁ hour ago in memory D1 having a memory address of 2048 words
In order to read GD(t-x ₁ ), the address of the memory D1 corresponding to the delay time x ₁ is specified. As a result, musical tone data from memory D1 x ₁ hour ago
GD(t-x ₁ ) is read. Then, this musical tone data GD (t-x ₁ ) is supplied to the adder SUM2,
In this adder SUM2, other memories D2 and D
3 output data and delay circuit 2000B, 20
It is added to the output data of the memories D4 to D6 and D7 to D9 of 00C, and is temporarily stored in the register R11 in the adder SUM2. In this case, memory D1
The read operation of the memories D1 to D9 is performed sequentially in time division from the memories D1 to D9, and when the read operation of the memory D1 is performed, no data is output from the other memories D2 to D9. Therefore, the contents written to register R11 in adder SUM2 are as follows:
Data GD read from memory D1 (t-x ₁ )
becomes. On the other hand, musical tone data read from memory D1
GD(t-x ₁ ) is multiplied by a coefficient K ₁₈ for amplitude level control in a multiplier M18, and then fed back to the input side of the memory D1. And this multiplication value K ₁₈・
GD(t-x ₁ ) is the register R at the current time t.
It is added to the data K ₁₇ · GD (t-j) temporarily stored in register R6, and the added value K ₁₇ · GD (t-j) + K ₁₈ · GD (t-x ₁ ) is temporarily stored in register R6. . Next, the musical tone data “K ₁₇・GD(t-
j)+K ₁₈ ·GD(t-x ₁ )" is written to the same address where the musical tone data GD(t-x ₁ ) x ₁ hours ago was stored. After this, register R
The contents of 6 are reset. The reason why the contents of register R6 are reset is because this register R6 will be used also for processing of the memory D2 system in the next stage. When the processing of the memory D1 system is completed in this way, the processing of the memory D2 system is then performed in the same manner. That is, memory D with 2048 word addresses
Musical tone data GD ( _t-
x ₂ ), the address of the memory D2 corresponding to the delay time x ₂ is specified. As a result, musical tone data GD (t-x ₂ ) sampled x ₂ hours ago is read from the memory D2. Then, this musical tone data GD(t-x ₂ ) is added to the contents of the register R11 (the contents read from the memory D1) GD(t-x ₁ ) in the adder SUM2, and the added value ``GD(t-x ₁ )+GD(t- _x2 )" is register R
11 is temporarily stored. On the other hand, musical tone data read from memory D2
GD (t-x ₂ ) is multiplied by a coefficient K ₁₈ for amplitude level control in the multiplier M19, and then stored in the memory D2.
is fed back to the input side. And its multiplication value
K ₁₉・GD (t−x ₂ ) is added to the value K ₁₇・GD (t−j) temporarily stored in register R5, and the added value “K ₁₇・GD (t−j) + K ₁₉・GD (t-x ₂ )"
is temporarily stored in register R6. The data stored in this register R6 is “K ₁₇・GD(t−j)+
K ₁₉・GD(t−x ₂ )” is the data GD x ₂ hours ago
(t-x ₂ ) is stored at the same address where it was stored. After this, the contents of register R6 are reset. Next, the processing of the memory D3 system is performed in the same manner as the processing of the memory D2 system. Therefore, at the stage when processing of the memory systems D1 to D3 is completed, the delay time of the memory system D3 is x ₃
Then, the contents stored in register R11 are GD (t-x ₁ ) + GD (t-x ₂ ) + GD (t-x ₃ ), and the contents stored in memory D3 are K ₁₇ · GD (t −j)+K ₂₀・GD(t−x ₃ ). Such processing is performed by the delay circuits 2000B and 200
The same operation is performed at 0C. Therefore, memory D in delay circuit 2000B
The delay time of each system of 4, D5, and D6 is
Assuming that x ₄ , x ₅ , x ₆ and the delay times of each system of memories D7, D8, and D9 in delay circuit 2000C are x ₇ , x ₈ , and x ₉ respectively, the delay time is 2000.
The contents of register R11 at the stage when all processing of A to 2000C are completed are RVD ¹ = ₉ 〓 〓 ⁿ⁼¹ GD (t-x _o ) = GD (t-x ₁ ) + GD (t-x ₂ ) + GD (
t-x ₃ ) + GD (t-x ₄ ) + GD (t-x ₅ ) + GD (t-x ₆ ) + GD
(t- _x7 )+GD(t- _x8 )+GD(t- _x9 ). As a result, following the initial reflected sound, reverberant sound with coarse delay time intervals and regularly changing amplitude level and delay time is obtained, as shown in FIG. Note that in FIG. 13, the reverberant sound only for the delay circuit 2000A is illustrated because the time relationship is complicated. The reverberant sound data RVD ¹ with a coarse delay time interval formed as described above is transmitted to the second reverberant sound forming unit 30.
00 is input. The second reverberation sound forming section 3000 includes a delay circuit 300 having an all-pass filter configuration with flat frequency characteristics.
0A, 3000B, and 3000C are provided in series. 3 delay circuits 3000A, 3000B, 30
00C is provided in series with the reverberant sound data RVD ¹ obtained in the first reverberant sound forming section 2000.
This is to form reverberant sound data RVD ² with closer delay time intervals. Therefore, each delay circuit 3000A, 30 in this second reverberation sound forming section 3000
The delay times of 00B and 3000C are the delay times of each delay circuit 2000A and 2 in the first reverberation sound forming section 2000.
The delay time is set shorter than the delay time of 000B and 2000C. And each delay circuit 3000A, 300
0B and 3000C have the same configuration except for the delay time setting. Therefore, in the figure, only the numbers of multipliers, registers, and memories are shown for delay circuits 3000B and 3000C, and the detailed configuration of only delay circuit 3000A is shown. First, the reverberant sound data RVD ¹ output from the first reverberant sound forming section 2000 is supplied to the register ^R12 of the delay circuit 3000A.
Before storing in register R12, data RVD ¹ (t-y ₁ ) written y ₁ hour ago is first read out from memory MD0 having a storage address of 512 words, which corresponds to a delay time y ₁ hour. The address of memory MD0 to be stored is specified. This allows memory MD
0 to y Data written ₁ hour ago RVD ¹ (t-
y ₁ ) is read. Next, this data RVD ¹ (t
-y ₁ ) is multiplied by a coefficient K ₃₀ for amplitude level control in the multiplier M30, and the multiplier value K ₃₀
RVD ¹ (ty ₁ ) is fed back to the input side of memory MD0. And then this return data K ₃₀・RVD ¹
(t-y ₁ ) and the data RVD ¹ (t) supplied from the first reverberation sound forming section 2000 at the current time t, and the added value "RVD ¹ (t) + K ₃₀ · RVD ¹ (t-
y ₁ )” is temporarily stored in register R12. next,
The address of the memory MD0 corresponding to the delay time _y1 is specified again, and the data ^RVD1 (t- _y1 ) written _y1 hours ago is read out from the memory MD0 again.
The read data RVD ¹ (t-y ₁ ) is stored in register R.
13 is temporarily stored. Next, the data temporarily stored in register R12 “RVD ¹ (t)+K ₃₀・
RVD ¹ (t−y ₁ )” and constant K ₂₉ for amplitude level control
are multiplied by the multiplier M29. and,
The multiplied value K ₂₉ {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ₁ )} is the value RVD ¹ temporarily stored in register R13.
(t-y ₁ ), and the added value RVD ¹ (t-y ₁ ) + K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ¹ )} is temporarily stored in register R13. . Next, the data “RVD” temporarily stored in register R12 is
(t)+K ₃₀・RVD ¹ (t-y ₁ )'' from the current time t.
Since it is used at the sampling time (t+y ₁ ) delayed by y ₁ hour, the data "RVD ¹ (t)+K ₃₀・
RVD ¹ (t- _{y 1} )" is the data RVD ¹ (t-
y ₁ ) is written to the same address where it was stored. When the processing by the delay circuit 3000A is completed in this way, the data stored in the register R13 RVD ¹ (t-y ₁ ) + K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ₁ )} is is sent to delay circuit 3000B, and this delay circuit 3
At 000B, the same processing as in the case of circuit 3000A is performed. Here, delay circuits 3000A, 3000B, 3
000C output data as RVD ^2A , RVD ^2B ,
Expressed as RVD ^2C , the delay time of circuit 3000B is
y ₂ and the delay time of circuit 3000C is y ₃ , the output data of registers R13, R15, and R17 of circuits 3000A, 3000B, and 3000C are as follows:
It is expressed by equations (4) to (6). RVD ^2A = RVD ¹ (t-y ₁ ) + K ₂₉・{RVD ¹ (t) + K ₃₀
・RVD ¹ (t-y ₁ )} RVD ^2A = RVD ¹ (t-y ₁ )+K ₂₉・{RVD ¹ (t)+K ₃₀
・RVD ¹ (t-y ₁ )} RVD ^2B = RVD ^2A (t-y ₂ )+K ₃₁・{RVD ^2A (t)+K ₃₂・R
VD ^2A (t-y ₂ )} RVD ^2A = RVD ¹ (t-y ₁ ) + K ₂₉・{RVD ¹ (t) + K ₃₀
・RVD ¹ (t-y ₁ )} RVD ^2B = RVD ^2A (t-y ₂ )+K ₃₁・{RVD ^2A (t)+K ₃₂・R
VD ^2A (t-y ₂ )} RVD ^2C = RVD ^2B (t-y ₃ )+K ₃₃・{RVD ^2B (t)+K ₃₄・R
VD ^2B (t-y ₃ )}...(4)...(5)...(6) And the output data of the delay circuit 3000C
RVD ^2C is output via the switch circuit SW as data for generating reverberant sound following the initial reflected sound. Here, each delay circuit 3000A, 3000B,
When the delay time of 3000 C is set in the relationship y ₁ > y ₂ > y ₃ , reverberant sound with dense delay time intervals can be formed as shown in FIG. That is, the delay circuit 3000A generates the first reverberation sound at a time interval y 1 shorter than the delay time interval of the first reverberation sound formation unit 2000 based on the reverberation sound data RVD ¹ with a coarse delay time interval formed by the first reverberation sound formation unit ₂₀₀₀ . 1 reverberant sound data RVD ^2A , and the delay circuit 3000B generates the second reverberant sound data at a time interval _y2 shorter than the delay time interval _y1 of the circuit 3000A.
Form RVD ^2B . Therefore, the delay circuit 300
As the reverberation sound formation process from 0A to 3000C progresses, reverberation sounds with dense delay time intervals are formed. In addition, the delay circuits 3000A, 3000B, 30
Registers R12, R14, R16 at 00C
Since it is not used until the next sampling period after the processing related to its own circuit is completed, it can be shared in a time-sharing manner. Next, the specific configuration and operation of the embodiment shown in FIG. 6 will be explained. In addition, in the following explanation,
The following description will be made assuming that the apparatus shown in FIG. 6 forms reverberation sound according to the function shown in FIG. 8 described above. Specific Configuration of the Embodiment The reverberation sound adding device of the embodiment shown in FIG. 6 is roughly divided into a storage section 19, a time information generation section 20, an address information generation section 30, and a calculation section 40. The storage section 19 corresponds to the delay digital memory DM in FIG. 9, and here is composed of a data memory 190 having a plurality of memory blocks and a latch 191. The data memory 190 uses a plurality of memory blocks to store one word (16 bits) of memories SD0 to SD15 and 512 words (one word
16 bits) memories MD0 to MD15 and 2048 word memories (one word is 16 bits) D0 to D15 are provided. And this memory SD0~SD1
5. The data to be stored in MD0 to MD15 and D0 to D15 is given from the calculation unit 40, and the storage address and read address of the data are determined by the address information DM.
specified by ADR, and each memory SD0~D
The data read from 15 is supplied to arithmetic unit 40 via latch 191. The time information generating section 20 corresponds to the delay length data memory DDM in FIG. 9, and includes a parameter designation circuit 200 and a delay length data memory 201. According to the instructions, each data delay memory D0 to D15, corresponding to each of the eight types of reverberation sounds (including early reflection sounds) with different reverberation characteristics,
Delay time information regarding MD0 to MD15 DLD ^m
It is configured to selectively output one of the types [n] (n: designates memories D0 to D15, MD0 to MD15, m: designates types 1 to 8). That is, as shown in FIG. 16, the delay length data memory 201 includes memory blocks MB (D0) to MB corresponding to the data delay memories D0 to D15 and MD0 to MD15, respectively.
(D15), MB (MD0) to MB (MD15), and each of these memory blocks MB (D0) to MB
(MD15) has eight memory addresses "0" to "7" corresponding to the eight types of reverberant sounds described above, and each memory block MB(D0) to MB(MD
15), each memory address “0” to “7” has different delay time information DLD ¹ [D0] to ^{DLD 8}
[D0], DLD ¹ [D1] ~ ^{DLD 8} [D1], ...
DLD ¹ [D15] ~ ^{DLD 8} [D15], DLD ¹ [MD0]
~DLD ⁸ [MD0],...DLD ¹ [MD15] ~DLD ⁸
[MD15] is stored in advance. Then, 3-bit parameter designation information PSL indicating the reverberation characteristics of the reverberant sound to be generated is supplied from the parameter designation circuit 200 as lower address information,
Furthermore, specify the 4-bit memory number information DL _o (n: 0 to 15) that specifies the memory number “0 to 15” of the memories MD0 to MD15 and D0 to D15, and the memory type “D, MD, SD”. 2-bit memory type information DL _k (k: D, MD, SD) is used as upper address information by the address information generation unit 30.
When supplied from the memory block (MB(D0) to MB(MD1) specified by the information DL _o and DL _k
5), the delay time information DLD ^m [n] stored in the storage address (one of "0" to "7") specified by the information PSL is read out, and the parameter specification is performed. The information is supplied to the address information generating section 30 as information defining the delay time relationship of reverberant sound having the desired reverberation characteristics specified by the circuit 200. Note that for memories SD0 to SD15, the delay time is fixed (1・T ₀ ), so this memory SD0
- Delay time information for SD15 is not required.
In addition, the parameter designation circuit 200 outputs, together with the parameter designation information PSL, 3-bit program selection information PSG for selecting a desired control program from among the eight types of control programs for forming reverberation sound. Ru. Next, the address information generation unit 30 generates delay time information DLD ^m [n] output from the time information generation unit 20.
Based on the program selection information PGS and the master clock pulse φ ₀ that determines the cycle of one step of the control program, address information DM/ADR for the data memory 190 for forming reverberant sound with desired reverberation characteristics is generated. It also generates various control signals to control the operation of each circuit, and includes a program memory 300, a program counter 301, and a program decode memory 30.
2. Control signal output register 303, selector 30
4, an address counter 305, a latch 306, a subtraction circuit 307, a maximum value detection circuit 308, and an address information output circuit 309. Eight types of control programs are stored in advance in the program memory 300 in order to form reverberant sounds with eight types of reverberation characteristics, and the parameter specifying circuit 200 determines which type of control program should be output.
It is designated by program selection information PGS starting from 0. Then, the contents of the designated control program are sequentially read out step by step by the output information PC of the program counter 301 that counts the master clock pulse φ ₀ . In this case, all the processes of the early reflected sound forming section 1, bandpass filter BPF, first reverberant sound forming section 2000, and second reverberating sound forming section 3000 explained in FIG. 7 are performed within one sampling period (T ₀ ). To finish, if the sampling frequency is 25KHz and the frequency of master clock pulse φ ₀ is 4.8MHz,
The number of steps in one control program is within 4800/25=192, and the contents of the 192-step control program are executed every sampling period _T0 .
As shown in Table 2, the control programs for each step are Type 1, Type 2, and Type 3, each step consisting of 16 bits of information.
Three types of content are prepared, and the formation of early reflection sound, filter processing, and reverberation sound formation are performed by appropriately combining the output order of these three types of control programs and the content of each bit information. .

[Table] In this case, the one-step control program consisting of 16 bits is the information OF・ADR _o , RG _o , DL _o ,
Control signal output register 303 like ADR [Kn]
There are two types: one is output as is through the memory write control signal WR1, and the other is decoded by the program decode memory 302 and output via the control signal output register 303, such as the memory write control signal WR1. The code OPC is given from program memory 300 to program decode memory 302. Note that details of the contents of Table 2 will be described later together with an explanation of the overall operation. On the other hand, the address counter 305 is connected to delay memories D0 to D15, MD0 to
Address counter corresponding to each MD15
AC (D0) ~ AC (D15), AC (MD0) ~ AC
(MD15). Each counter AC(D0) to AC(D
15), AC(MD0) to AC(MD15) are selectively put into an operating state according to memory number information DL _o and memory type information DL _k . Information DL _o and
Address counter activated by DL _k
AC (n) (n: D0 to D15, MD0 to MD15)
The count output information ADR[n] is supplied to the address information output circuit 309 via the latch 306 and also to the subtraction circuit 307. In this case, the output information ADR of address counter AC(n)
[n] is memory D0 to D15, MD0 to MD15
Since the memories D0 to D15 have an address length of 2048 words, they are composed of 11 bits so that an address range of up to 2048 words can be specified. Note that the address counter 305 is composed of RAM. The arithmetic circuit 307 calculates the output content of the address counter AC(n) input via the latch 306.
Subtract “1” from ADR[n] and apply the subtracted value “ADR[n]-1” to the next sampling period (t+
It is fed back to the A side input of the selector 304 for use in step 1). At the same time, the maximum value detection circuit 308
supply to. The maximum value detection circuit 308 corresponds to the detection circuit _MXD in FIG _.
Information “ADR[n]-1” which is obtained by subtracting “1” from [n]
When it is detected that has reached the maximum value (all bits are "1"), it outputs a select control signal SLB that causes the selector 304 to select the B side input. In the selector 304, the subtraction circuit 30 is connected to the A side input.
7's output information "ADR[n]-1" is input, and B
Output information DLD ^m [n] of the delay length data memory 201 is input to the side input, and its output is supplied to the data input of the address counter 305 and input to the address counter Ac(n) specified by the information DL _o and DL _k . On the other hand, it is configured to be written (preset) by a write control signal WR3. Therefore, in the address counter Ac(n) specified by the information DL _o and DL _k , the current value ADR[n ] minus “1” is the value “ADR
[n]-1" is written, and the output information ADR[n] decreases toward "0" as time passes. However, when the value "ADR(n)-1" reaches the maximum value, the select control signal SLB is generated from the maximum value detection circuit 308, so the delay time information DLD is sent to the address counter AC(n) via the selector 304. ^m [n] is input and written.
Therefore, the contents of the address counter AC(n) become "DLD ^m [n]" due to the generation of the select control signal SLB.
After that, it changes sequentially toward "0" as the sampling time passes. That is, selector 304, address counter 305,
In the part consisting of the latch 306, the subtraction circuit 307, and the maximum value detection circuit 308 _, the delay time corresponding to the delay time information DLD ^m [n] is equal to the address counter AC(n) specified by the information DL o and DL _k . Address information ADR[n] that goes around in a cycle is formed. This address information ADR[n] is supplied to the address information output circuit 309. The address information output circuit 309 is the memory SD0
~SD15, memory D0~D15, memory MD0
- Address information for reading and writing information to the MD 15 is output. This address information output circuit 309 outputs data from memory D0.
i _o Read out time-delayed information and generate early reflection sound ECH (t)
When forming address information ADR [D0 _] regarding memory D0 and ₁₁ -bit address information OF· _{ADR o} (= OF・ADR ₁ ~OF・
ADR ₁₀ : The sum of the value (output from the control signal output register 303) is used as the lower address information, and the memory number information DL _o (=DL ₀ ) and memory type information DL _k (=DL _D ) are added to the upper part. , this set of information ADR[D0]+OF·ADR _o , DL _o , DL _k is output as address information DM·ADR. Also,
Musical sound data GD(t) sampled at the current time
When writing to memory D0, output information ADR of address counter AC (D0) corresponding to memory D0
[D0] is the lower address information, and information DL _o (=DL ₀ ) and DL _k specifying the memory D0 above it
(=DL _D ) and add this set of information ADR [D
0], DL _o , and DL _k as address information DM/ADR. Furthermore, when writing and reading data to and from the memories SD0 to SD15, all bits of the lower address information are set to "0", and information DL _o (=
DL ₀ to DL ₁₅ ) and DL _k (=DL _SD ) are added and output as address information DM/ADR. Also,
When forming reverberant sounds RVD ¹ and RVD ² , address counters AC(D1) to AC(D1) corresponding to memories D1 to D15 and MD0 to MD15, respectively, are used.
5), AC (MD0) to AC (MD15) output information ADR [D1] to ADR [D15], ADR [MD0]
~ADR [MD15] is the lower address information, information DL _o and DL _k are added to the upper part, and these 1
Set information ADR [n], DL _o , DL _k as address information
Output as DM/ADR. In this case, the information DL _o
and information below DL _k ADR [n] + OF・ADR _o
When it is necessary to add the control signal output register 303
Control pulse GP1 is output from. Also, information
When all bits of the lower address information added to the lower order of DL _o and DL _k are to be set to "0", a control pulse GP2 is output from the control signal output register 303. Note that the address information output circuit 309 outputs information
It has internal registers to temporarily store DL _o and DL _k . Next, the calculation unit 40 stores the memories D0 to D15,
It controls the amplitude level of data stored in MD0 to MD15 and SD0 to SD15 and data read from each memory, and includes a coefficient memory 400, a selector 401, an arithmetic circuit 402, a temporary register 403, and a latch 404. Like the delay length data memory, the coefficient memory 400 has eight memory blocks corresponding to eight types of reverberant sounds with different reverberation characteristics, and each memory block has the memory blocks necessary to form each type of reverberant sound. A set of coefficients K _o (n: 1 to 64) is stored in advance. And the parameter specification circuit 200
When the parameter specification information PSL is supplied from the control signal output register 303 and the address information ADR [K _o ] specifying the coefficient K _o is supplied from the control signal output register 303, the information
Information about memory blocks specified by PSL
The coefficient K _o is read from the address specified by ADR [K _o ] and is supplied to the arithmetic input A of the arithmetic circuit 402 . The selector 401 inputs sampled musical tone data GD(t) to the A side input.
is input, the read data MRD from the storage unit 19 is input to the B side input, and the latch 40 is input to the C side input.
The output data RGD of the temporary register 403 is input through 4, and these input data
GD(t), MRD, and RGD are the select control signal SL1 output from the control signal output register 303.
(2-bit configuration), one of them is selected and supplied to the calculation input (X) of the calculation circuit 402. The arithmetic circuit 402 has a coefficient memory 4 at the arithmetic input (A).
The coefficient K _o read from 00 is input, the output data RGD of the temporary register 403 is input to the calculation input (B) via the latch 404, and the selected output data (SPD) of the selector 401 is input to the calculation input (X).
(t), MRD, RGD) are input, and the calculation control signal is output from the control signal output register 303.
With CTL (3-bit configuration), (Y)=(A)・(X)+(B)...(7-1) (Y)=(X)+(B)...(7-2) (Y ) = (X) ... (7-3) (Y) = (B) ... (7-4) (Y) = (0) ... (7-5) Y) in the temporary register 403, storage section 19, output register 50
0. The temporary register 403 stores the early reflection sound.
ECH (t), the calculated value (Y) of the calculation circuit 402 in the process of forming the reverberant sounds RVD ¹ and RVD ² is temporarily stored, and the stored contents are used as register output data RGD to input the C side of the selector 401 and the calculation circuit 4
It is fed back to the calculation input B of 02, and has 32 registers R0 to R31 specified by register designation information RG _o (n: 0 to 31) of 5 bits.
Input data is written into registers (R0 to R31) specified by information RG _o under the control of write control signal WR1. Next, the output register 500 is connected to the arithmetic circuit 402.
The instantaneous value ECH (t) of the early reflected sound obtained as the calculated value (Y) of The signal is supplied to the DA converter 12 in FIG. 1 via the converter 501. Note that the selection control signal SL1 in the selector 401 and the calculation control signal CTL in the calculation circuit 402 are included in the operation code OPC output from the control signal output register 303. Next, the operation of the above configuration will be explained. Operation explanation a Early reflection sound formation operation (1) First, in order to write the musical sound data GD (t) sampled at the current time t to the memory D0, SL1; SELECT (A) CTL; (Y) = (X) The select control signal SL1 and calculation control signal CTL with the contents shown are outputted to the control signal output register 30 as the operation code OPC.
Output from 3. As a result, the selector 401 transfers musical tone data GD(t) to the arithmetic circuit 4.
02 calculation input (X). Further, the arithmetic circuit 402 outputs musical tone data GD(t) inputted to the arithmetic input (X) as a calculated value (Y). (2) Next, after specifying the address of memory D0 corresponding to the current sampling time (t),
The output data of the arithmetic circuit 402 is placed at this address.
In order to write GD(t), the memory type information DL _k with the contents indicated by DL _o ; DL ₀ DL _k ; DL _D WR4; “1” (WRITE) L3; “1” (LATCH), and the write control signal WR4. , the latch control signal L3 is used as the operation code OPC, and the memory number information DL _o is used as the control signal output register 30.
Output from 3. As a result, the output information ADR of address counter AC (D0) corresponding to memory D0
[D0] is musical tone data GD(t) at current time t
is latched in latch 306 as lower address information for writing. This latched lower address information ADR [D0] is
In the address information output circuit 309, memory number information DL _o (=DL ₀ ) and memory type information DL _k (=DL _D ) are added to the upper part of the address information output circuit 309 to write address information DM/ADR of musical tone data GD(t) to memory D0. is output as Thereby, the musical tone data at the current time t which is applied to the data input of the memory D0 of the data memory 190 via the arithmetic circuit 402.
GD(t) is written to the address corresponding to the current time t by the write control signal WR4. (3) Next, in order to clear the register R0 that stores the composite value of early reflection sounds for each sampling time, the contents indicated by RG _o ; R0 CTL; (Y) = 0 WR1; “1” (WRITE) The calculation control signal CTL and write control signal WR1 are the operation code.
Register number information RG _o is also output from the control signal output register 303 as OPC. As a result, "0" is written into register R0. That is, register R0 is cleared. (4) Next, in order to form the first reflected sound ECH ₁ , the memory with the contents shown as OF・ADR _o ;OF・ADR ₁ DL _k ;DL _D GP1; “1” L2; “1” (LATCH) The type information DL _k , control pulse GP1, and latch control signal L2 are used as the operation code OPC, and the address information OF/ADR ₁ corresponding to the delay time i ₁ of the first reflected sound ECH ₁ is used as the control signal output register 30.
Output from 3. In this case, the address information output circuit 309 holds the memory number information DL _o (=DL ₀ ) in step (2). As a result, the address information output circuit 30
9 adds the address information ADR [D0] latched in the latch 306 and the address information OF·ADR ₁ corresponding to the delay time i ₁ , sets the added value as lower address information, and sets the memory number information DL _o ( = DL ₀ ), memory type information DL _k (=
With DL _D as upper address information, musical tone data GD written from memory D0 i ₁ hour ago (t-i ₁ )
Output as address information DM/ADR for reading. As a result, from memory D0
Musical tone data GD (t-i ₁ ) from _one hour before i is read out, and this read data GD (t-i ₁ ) is latched in latch 191 by latch control signal L2. (5) Next, latch 40 the current value of register R0.
4, the latch control signal L1 with the contents indicated by RG _o ; R0 L1; "1" (LATCH) is output as an operation code and the register number information RG _o is output from the control signal output register 303 . This causes the current value of register R0 to be transferred to latch 404 and stored. (6) Next, musical tone data GD (t-i ₁ ) from i ₁ hour ago
is multiplied by the coefficient K ₁ for amplitude level control, and _{the instantaneous value K 1 ·} GD (t-
i ₁ ), select control signal SL1 shown as ADR [K _o ]; ADR [K ₁ ] SL1; SELECT(B) CTL; (A)・(X)+(B)=(Y), calculation Control signal CTL serves as operation code OPC and address information for reading constants.
ADR [K _o ] is the control signal output register 303
is output from. As a result, the first
The coefficient K ₁ related to the reflected sound ECH ₁ is read out and supplied to the calculation input (A) of the calculation circuit 402 . In addition, the selector 401 selects the musical tone data GD (t-i ₁ ) of i ₁ hour ago supplied from the latch 191 to the B-side selection input, and
(t-i ₁ ) is the calculation input (X) of the calculation circuit 402
supply to. In addition, the arithmetic circuit 402 (Y)=(A)・(X)+(B)=K ₁・GD(t−i ₁ )+
Perform the operation indicated by [R0]. In this case, the contents of register R0 were cleared in step (3) above, so here we will discuss the first reflected sound.
The instantaneous value K ₁ ·GD (ti ₁ ) regarding ECH ₁ is obtained as the calculation value (Y) of the calculation circuit 402. (7) Next, the instantaneous value K ₁・GD of the first reflected sound ECH ₁
(t-i ₁ ) is transferred to register R0 and stored, write control signal WR1 with the content indicated by RG _o ; R0 WR1; "1" (WRITE) is used as operation code OPC and register number information RG. _o is control signal output register 3
Output from 03. As a result, the output data (Y) = K ₁ · GD (ti ₁ ) of the arithmetic circuit 402 is transferred to the register R0.
written to. By completing the steps up to this point, the instantaneous value _K1 ·GD(t- _i1 ) of the first reflected sound _ECH1 is obtained in the register R0. (8) Next, 2nd reflected sound ECH ₂ ~ 10th reflected sound
Instantaneous value K ₂ · GD (t-i ₂ ) for ECH ₁₀ ~
K ₁₀・GD (t−i ₁₀ ) is the step (4) to (7) mentioned above.
It is formed in the same way. Therefore, when the operation of step (7) regarding the 10th reflected sound ECH ₁₀ is completed, the first reflected sound is stored in the register R0.
Total of instantaneous values of ECH ₁ to 10th reflected sound ECH _{10 10 〓} ⁿ⁼¹
K _o ·GD (t-i _o ) is obtained. And this total ₁₀ 〓 ⁿ⁼¹ K _o・GD (t−i _o ) is the output register 5
00 by write control signal WR2 and transferred to attenuator 501. b Filter operation (1) First, to read musical tone data GD (t-j) from memory D10 from j hours ago, DL _o ; DL DL _k ; DL _D L3; "1" (LATCH) L2; "1" Memory type information DL _k with the contents indicated by (LATCH), latch control signals L3 and L2 are output as an operation code OPC, and memory number information DL _o is output from the control signal output register 303 . As a result, the output information of address counter AC (D10) corresponding to memory D10
ADR [D10] is musical tone data GD j hours ago
(t-j) is latched into latch 306 as lower address information for reading. And this latched lower address information
ADR [D10] is the address information output circuit 3
In 09, memory number information DL _o
(=DL ₁₀ ) and memory type information DL _k (=
DL _D ) is added to the memory D10 of the data memory 190, and musical tone data GD(t-j) is added.
The read address information is output as DM/ADR. As a result, j
The previous musical tone data GD (t-j) is read out, and this read data GD (t-j) is latched in the latch 191 by the latch control signal L2. (2) Next, in order to write the musical tone data GD (t) sampled at the current time t to the same address as the read address of the data GD (t-j), SL1; SELECT (A) CTL; (Y) = ( The select control signal SL1 and calculation control signal CTL with the contents indicated by X) are sent to the control signal output register 30 as the operation code OPC.
Output from 3. As a result, the selector 401 transfers musical tone data GD(t) to the arithmetic circuit 4.
02 calculation input X. Further, the arithmetic circuit 402 outputs musical tone data GD(t) inputted to the arithmetic input X as a calculated value (Y). (3) Next, musical tone data GD(t) is stored in memory D1.
To write to 0, DL _o ; DL ₁₀ DL _k ; DL _D WR4; “1” (WRITE) L3; “1” (LATCH) Memory type information DL k of the contents indicated by DL _k , write control signal WR4, latch control The signal L3 is used as the operation code OPC, and the memory number information DL _o is used as the control signal output register 30.
Output from 3. As a result, the output information of address counter AC (D10) corresponding to memory D10
ADR [D10] is musical tone data at current time t
It is latched in latch 306 as lower address information for writing GD(t). And this latched lower address information
ADR [D10] is the address information output circuit 3
In 09, memory number information DL _o
(=DL ₁₀ ) and memory type information DL _k (=
DL _D ) is added to write address information of musical tone data GD(t) to memory D10.
Output as DM/ADR. This results in
Data memory 190 via arithmetic circuit 402
Musical tone data GD(t) at the current time t, which is applied to the data input of the memory D10, is written to the address corresponding to the current time t by the write control signal WR4. (4) Next, in the low pass filter LPF,
To calculate [R1] + K ₁₁ · GD (t-j) using the contents of register R1, coefficient K ₁₁ , and musical tone data GD (t-j) from j hours ago, and store this calculated value in register R1 again. , First, the latch control signal L1 indicated by the contents _of RG _o ;
3 and the contents of register R1 are transferred to latch 404. (5) Next, in order to calculate K ₁₁・GD(t−j), ADR [K _o ]; ADR [K ₁₁ ] SL1; SELECT(B) CTL; (Y)=(A)・(X ) + (B) Select control signal SL1 with the content shown as
Arithmetic control signal CTL is the operation code
As OPC, address information ADR [K _o ] for reading constants is used as control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
K ₁₁ is read out and supplied to calculation input A of calculation circuit 402 . Further, the selector 401 selects the musical tone data GD (t-j) latched in the latch 191 in the previous step b-(1), and supplies it to the calculation input (X) of the calculation circuit 402. Thereby, the calculation circuit 402 performs the calculation (Y)=(A)·(X)+(B)=K ₁₁ ·GD(t−j)+R1. In this case, the contents of register R1 were cleared at the stage when the filter processing at the previous sampling time (t-1) was completed, so in this step, _K11・GD
(t-j) is obtained as the calculated value (Y). (6) Next, this calculated value (Y) = K ₁₁・GD (t-
j) in the register R1 _, the write control signal WR1 indicated by the contents of RG _o ;
Output from 03. As a result, output data _K11 ·GD(tj) of the arithmetic circuit 402 is stored in the register R1. (7) Next, in order to read musical tone data GD (t-j-1) of (j-1) time ago from memory SD0, DL _o ; DL ₀ DL _k ; DL _SD GP2; "1"L2;" 1” (LATCH), the memory type information DL _k , the latch control signal L2, and the gate pulse signal GP2 are used as the operation code OPC, and the memory number information DL _o is used as the control signal output register 3.
Output from 03. Then, the address information output circuit 309 sets all bits of the lower address information to "0" and stores memory number information DL _o (=DL ₀ ) and memory type information DL _k in the upper part.
(DL _SD ) is added and output as address information DM/ADR for memory SD0. As a result, the musical tone data GD (t-j-1) of (j-1) time ago is read from the memory SD0 and latched in the latch 191. (8) Next, the contents of register R1 K ₁₁・GD(t−
J), coefficient K ₁₂ , and musical tone data GD (t-j-1) latched in latch 191, calculate K ₁₂ GD (t-j-1) + [R1], and store this calculated value in register R1. In order to store it again, first, the latch control signal L1 with the contents indicated _by RG _o ; R1 L1;
3 and the contents of register R1 _K11・
GD(t-j) is transferred to latch 404. (9) Next, in order to calculate K ₁₂ · GD (t-j-1) + [R1], ADR [K _o ]; ADR [K ₁₂ ] SL1; SELECT (B) CTL; (Y) = The signals SL1 and CTL with the contents shown by (A) and (X) + (B) are used as the operation code OPC, and the address information ADR (K _o ) is used as the control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
_K12 is read out and is the calculation input to the calculation circuit 402.
(A) is supplied. In addition, the selector 401 selects the tone data latched in the latch 191.
GD (t-j-1) is selected and the arithmetic circuit 40
It is supplied to the calculation input (X) of No.2. As a result, the arithmetic circuit 402 calculates (Y)=(A)・(X)+(B)=K ₁₂・GD(t−j−1)+ _K11・GD(t−
j) Outputs the calculated value (Y). This calculated value (Y) is then stored in registers R1 and R2 in the next step. As a result, the contents of register R1 and register R2 become as follows: [R1]=[R2]= _K12 *GD(t-j-1)+ _K11 *GD(t-j). (10) Next, based on the contents of register R2, coefficient K ₁₃ , and musical tone data GD (t-j-1) of (j-1) time ago stored in memory SD0,
In order to perform the operation _K13・GD(t-j-1)+[R2], first, the contents of register R2 are latch 4.
04, the contents of register R2 are transferred to _K12.04 in the same manner as in step b-(8) above.
GD(t−j−1)+K ₁₁ ·GD(t−j) is transferred to latch 404. (11) Next, read out the coefficient K ₁₃ and calculate K ₁₃・GD(t−
In order to calculate j-1) + [R2], ADR [K _o ]; ADR [K ₁₃ ] SL1; SELECT (B) CTL; (Y) = The signals SL1 and STL with the contents shown by (A) and (X) + (B) are used as the operation code OPC, and the address information ADR [K _o ] is used as the control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
_K13 is read out and is the calculation input to the calculation circuit 402.
(A) is supplied. In addition, the selector 401 selects the tone data latched in the latch 191.
GD (t-j-1) is selected and the arithmetic circuit 40
It is supplied to the calculation input X of No.2. As a result, the arithmetic circuit 402 calculates (Y)=(A)・(X)+(B)=K ₁₃・GD(t−j−
1) +K ₁₂・GD (t-j-1) +K ₁₁・GD (t-
j) Outputs the calculated value (Y). This calculated value (Y) is then stored in register R2 in the next step, and is supplied to the high pass filter HPF via register R2. (12) In the final step in the low-pass filter LPF, the contents of register R1 are stored in the memory SD
0 and use it at the next sample time (t+1), first write the contents of register R1 to ``K ₁₂ · GD (t-j-1) + K ₁₁ · SPD (t-
j)” is transferred to the latch 404 in the same manner as in step b-(8) above, and then the arithmetic circuit 4
_{. _}
GD(t-j)" is written to the memory SD0.
This write operation is executed by the operation code indicated by DL _o ; DL ₀ DL _k ; DL _SD GP2; “1” WR4; “1” (WRITE)
This is performed by outputting OPC and memory number information DL _o from the control signal output register 303 . After the operation of the low-pass filter LPF is completed, the operation of the high-pass filter HPF is performed next, but a description of the operation of this high-pass filter HPF will be omitted. Next, the operation of forming the reverberant sound RVD ¹ with coarse delay time intervals will be explained. c Formation operation of reverberant sound RVD ¹ (1) First, the data GD(t-j) stored in register R4 of the high-pass filter HPF is multiplied by a coefficient _K17 , and the multiplied value _K17・GD(t-j) is stored in the register. In order to store it in R5, the latch control signal L1 and register number information RG _o with the contents indicated by RG _o ; R4 L1; "1" (LATCH) are output from the control signal output register 303, and the contents of register R4 are
GD(t-j) is transferred to latch 404. (2) Next, to calculate K ₁₇ · GD (t-j), ADR [K _o ]; ADR [K ₁₇ ] SL1; SELECT (C) CTL; (Y) = (A) · (X) Select control signal SL1 with the content shown in
The arithmetic control signal CTL and the address information ADR [K _o ] for reading coefficients are output from the control signal output register 303 . This allows the coefficients to be saved from the coefficient memory 400.
_K17 is read out and is the calculation input to the calculation circuit 402.
(A) is supplied. In addition, the selector 401 selects the data GD latched in the latch 404.
(tj) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)=K ₁₇ ·GD(t−j). This calculated value (Y) is stored in register R5 in the next step. (3) Next, read musical tone data GD (t-x ₁ ) x ₁ hours ago from memory D1 of data memory 190, add this data GD (t-x ₁ ) and the current value of register R11, In order to store the added value in the register R11 again, first, the latch control signal L3 with the content shown as DL _o ; DL ₁ DL _k ; DL _D L3; "1" (LATCH) L2; "1" (LATCH) is L2
Then, memory number information DL _o and memory type information DL _k are output from the control signal output register 303 . As a result, the output information ADR [D
1] is latched in latch 306 as lower address information for reading musical tone data GD (t-x ₁ ). This lower address information ADR [D1] is then sent to the address information output circuit 30.
9, memory number information DL _o and memory type information DL _k are added to the higher order, and outputted to the data memory 190 as address information DM/ADR of the memory D1. As a result, the musical tone data GD (t-x ₁ ) x ₁ hours ago is read out from the memory D1, and the latch 191
is latched to. (4) Next, in order to add this read data GD (t-x ₁ ) and the current value of register R11,
After the contents of register R11 are transferred to the latch 404, the select control signal SL1 and calculation control signal CTL with the contents shown by SL1; SELECT (B) CTL; (Y) = (X) + (B) are output as control signals. It is output from register 303. Then, the selector 401 selects the musical tone data GD(t-x ₁ ) latched in the latch 191.
Select the calculation input (X) of the calculation circuit 402
supply to. As a result, the arithmetic circuit 402 outputs the arithmetic value (Y) expressed as (Y)=(X)+(B)=[R11]+GD(t- _x1 ). In this case, the contents of the register R11 are cleared at the stage when the operation at the previous sampling time (t-1) is completed. Therefore, the calculated value (Y) in step (4) is GD(t-
x ₁ ). Thereafter, the calculated value (Y) is transferred to and stored in register R11. (5) Next, musical tone data GD (t
−x ₁ ) and multiply it by the coefficient K ₁₈ ,
Furthermore, in order to store the added value of the multiplied value K ₁₈ · GD (t-x ₁ ) and the content "K ₁₇ · GD (t-j)" of the register R5 again in the register R6, first, the above-mentioned c-(1 ), the content of register R5 is "K ₁₇・GD(t-j)".
is transferred to latch 404. (6) Next, the musical tone data GD (t-x ₁ ) latched in the latch 191, the data "K ₁₇ GD (t-j)" latched in the latch 404,
Due to the coefficient K ₁₈ , (Y) = K ₁₈・GD (t-x ₁ ) + K ₁₇・GD (t-
j) To perform the calculation, ADR [K _o ]; ADR [K ₁₈ ] SL1; SELECT (B) CTL; select control signal with the content shown as (Y) = (A)・(X) + (B) SL1,
The arithmetic control signal CTL and the address information ADR [K _o ] for reading coefficients are in the control signal register 30.
Output from 3. This allows the coefficients to be saved from the coefficient memory 400.
_K18 is read and is the calculation input to the calculation circuit 402.
(A) is supplied. In addition, the selector 401 selects the tone data latched in the latch 191.
GD (t-x ₁ ) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 outputs (Y)=(A)*(X)+(B)= _K18 *GD(t- _x1 )+ _K17 *GD(t-j). This calculated value (Y) is then transferred to the memory D via register R6 in the next step.
1 is written to the address corresponding to the current time t. After this, the register R6 is cleared in order to perform the processing of the memory D2 system. (7) Next, processing regarding each system of memories D2 to D9 is performed in the same manner as steps c-(3) to c-(6) described above. And memory D1~
When the processing of each system of D9 is completed, information regarding the reverberant sound RVD ¹ expressed as RVD ¹ (t)= ₉ 〓 ⁿ⁼¹ GD (t−x _o ) is obtained in the register R11. Next, the operation of forming reverberant sound RVD ² with dense delay time intervals will be explained. d Formation operation of reverberant sound RVD ² (1) First, in order to read the reverberant sound data RVD ¹ (t-y ₁ ) of y ₁ hour ago from memory MD0, DL _o ; DL ₀ DL _k ; DL _MD L3; 1” (LATCH) L2; Latch control signals L3, L1 with contents indicated by “1” (LATCH)
Then, memory number information DL _o and memory type information DL _k are output from the control signal output register 303 . As a result, the address information DM/ADR for the memory MD0 is formed in the address information output circuit 309 in the same manner as in step c-(3) above, and the address information DM/ADR is formed from the memory MD0.
Data RVD ¹ (t-y ₁ ) of _one hour before y is read. And this data RVD ¹ (t-y ₁ )
is latched by latch 191. (2) Next, the data latched in latch 191
Using RVD ¹ (t-y ₁ ), the output data RVD ¹ (t) of register R11, and the coefficient K ₃₀ , calculate K ₃₀ · RVD ¹ (t-y ₁ ) + RVD ¹ (t), and store the calculated value in the register. In order to store it in R12, first, the output data RVD ¹ (t) of register R11 is transferred to latch 404, and then ADR [K _o ]; ADR [K ₃₀ ] SL1; SELECT (B) CTL; (Y) = Select control signal SL1 with contents shown by (A)・(X)+(B),
Arithmetic control signal CTL and address information ADR [K _o ] for reading coefficients are output from control signal output register 303 . As a result, the arithmetic circuit 402 has the above-mentioned c
- Similarly to step (6), the coefficient K ₃₀ is supplied to the calculation input (A), and the data RVD ¹ (t-
y ₁ ) is supplied to the calculation input (X). As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)+(B)=K ₃₀ ·RVD ¹ (t−y ₁ )+RVD ¹ (t). This calculated value (Y) is then stored in register R12 in the next step. (3) Next, the contents of register R12 “K ₃₀・
In order to multiply "RVD ¹ (t-y ₁ ) + RVD ¹ (t)" by the coefficient K ₂₉ , the contents of register R12 are first transferred to latch 404, and then ADR [K _o ]; ADR [K ₂₉ ] SL1; SELECT(C) CTL; Select control signal SL1 with the content shown by (Y) = (A)・(X),
The arithmetic control signal CTL and address information ADR [K _o ] for reading coefficients are output from the control signal output register 303 . As a result, the calculation circuit 402 has a coefficient K ₃₀
is supplied to the calculation input (A), and data "K ₃₀ ·RVD ¹ (t-y ₁ )+RVD ¹ (t)" is supplied to the calculation input (X). As a result, the arithmetic circuit 402 calculates (Y)=(A)・(X)=K ₂₉・{K ₃₀・RVD ¹ (t−y ₁ )+RVD ¹
(t)} The calculated value (Y) is output. This calculated value (Y) is stored in register R13 in the next step. (4) Next, add the contents of register R13 and the data y ₁ hour ago RVD ¹ (t-y ₁ ) (latched in latch 191 in step d-(1) above), and In order to store the added value in register R13 again, the contents of register R13 " _K29 .
After {K ₃₀ · RVD ¹ (t-y ₁ ) + RVD ¹ (t)}'' is transferred to latch 404, SL1; SELECT (B) CTL; (Y) = (B) + (X) Content selection control signal SL1,
A calculation control signal CTL is output from the control signal output register 303. As a result, the arithmetic circuit 402 calculates (Y)=(B)+(X)= ^RVD1 (t- _y1 )+ _K29・{ _K30・^RVD1 (t- _y1 )+ ^RVD1
(t)} The calculated value (Y) is output. This calculated value (Y) is stored in the register R13 in the next step and output as reverberation sound information RVD ^2A . (5) Next, the contents of register R12 “K ₃₀・
RVD ¹ (t-y ₁ ) + RVD ¹ (t)'' is used at the sampling time (t + y ₁ ) delayed by y ₁ hour, so the contents of register R12 are written to the address corresponding to the current time t in memory MD0. . (6) After this, the reverberation sound is denser than the y ₁ hour interval.
RVD ^2B and RVD ^2C are formed in the same manner. In the embodiment shown in FIG. 6 (FIG. 7), a band pass filter BPF is provided, but this may be omitted if necessary.
In addition, as shown in the functional block diagram of FIG. 18, the output data of the memory D10 is divided into three series of frequency bands by a high pass filter HPF, a band pass filter BPF, and a low pass filter LPF. Different reverberation sounds may be generated for each frequency band. This can be easily achieved by simply changing the contents of the control program. As described above, since the reverberation sound adding device of this embodiment utilizes digital memory as a delay element, the S/N ratio does not decrease even if the reverberation time is increased, and the reverberation sound quality is the same as that of natural reverberation. can generate reverberant sound. Another advantage is that the reverberation time can be freely changed by changing the address interval of the digital memory. Further, there are advantages in that one arithmetic circuit can be shared in a time-division manner and the configuration can be simplified. As explained above, since the electronic musical instrument according to the present invention has a plurality of musical tone series, it is possible to arbitrarily select the series to which reverberant sound is to be added.
Reverberation can be freely added or omitted depending on the musical timbre of each series. Further, the reverberation sound adding means includes a reverberation characteristic indicating means for selectively instructing reverberation characteristics of the reverberant sound from among a plurality of reverberation characteristics, and a reverberant sound corresponding to each of the reverberation characteristics that can be specified by the reverberation characteristic indicating means. a control program memory that stores a plurality of control programs for the specified reverberation characteristics and outputs a control program corresponding to the specified reverberation characteristics; and a parameter generation means that outputs parameters related to each specified reverberation characteristic according to the control program; At least a control means for outputting a memory control signal for controlling writing/reading and addressing of the memory in accordance with the above-mentioned control program and an arithmetic control signal for controlling arithmetic operations; and a memory which has a plurality of addresses and which writes and reads the output of the calculation means in accordance with the memory control signal, and a combination of the two. and a reverberation sound forming means that adds reverberation characteristics instructed by the instruction means to the digital musical tone signal inputted by the instruction means and outputs the resultant signal.Since it has a digital structure, it is possible to improve the S/N ratio with a simple structure. It has excellent effects such as being able to form a good reverberant sound, and changing the reverberation characteristics very easily even during the performance, further enhancing the performance effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the electronic musical instrument according to the present invention, FIGS. 2 and 4 are circuit diagrams showing specific examples of the musical tone data accumulator shown in FIG. 1, and FIG. 3 is its operation. 5 is a diagram showing an example of a circuit for changing the sampling rate of musical sound data supplied to the reverberation sound adding device, and FIG. 6 is a diagram showing one example of the reverberation sound adding device used in the present invention. 7 is a functional block diagram functionally representing the embodiment of FIG. 6, FIGS. 8 and 9 are block diagrams showing the basic configuration of the delay circuit, and FIG. 10 is a block diagram showing the basic configuration of the delay circuit. FIG. 8 is a time chart for explaining the operation of the delay circuit, FIG. 11 is a characteristic diagram of the early reflected sound generated in the embodiment of FIG. 6, and FIG. 12 is the frequency of the delay circuit having a comb filter configuration. Figures 13 and 14 are diagrams showing the characteristics of reverberant sound generated in the embodiment of Figure 6. Figure 15 is a diagram showing the structure of the data memory in the embodiment of Figure 6. This figure shows the structure of the delay length data memory in the embodiment of FIG. 6, and FIG.
FIG. 18 is a functional block diagram showing another embodiment of the reverberation sound adding device used in the present invention. 1... Upper keyboard, 2... Lower keyboard, 3... Pedal keyboard, 6... Musical tone signal generation circuit, 8... Musical tone data accumulator, 9... Musical tone data selection circuit, 1
0...Reverberation sound addition keyboard selection circuit, 11...Reverberation sound addition device, 19...Storage unit, 20...Time information generation unit, 30...Address information generation unit, 40...Arithmetic unit, 1000...Initial stage Reflected sound forming section, 2000
...first reverberant sound forming section, 3000...second reverberant sound forming section.

Claims (1)

[Scope of Claims] 1. Musical sound signal generation means that generates a plurality of series of digital musical sound signals having different musical sound characteristics such as timbre, and a digital reverberation sound addition device that adds reverberation sound to an input digital musical sound signal and outputs the resultant signal. and selecting means for selectively supplying a desired series of digital musical sound signals from the plurality of series of digital musical sound signals to the reverberant sound adding means, and the reverberant sound adding means has reverberation characteristics of the reverberant sound. a reverberant sound instructing means for selectively instructing from a plurality of reverberant characteristics, and a plurality of control programs for forming reverberant sounds corresponding to each of the reverberation characteristics that can be instructable in the reverberant sound instructing means; a control program memory for outputting a control program corresponding to the reverberation characteristics specified by the characteristic indication means; a reverberation sound forming means including a calculation means and a data memory having a plurality of addresses; parameter generating means for generating a parameter related to delay time and a parameter related to calculation coefficient corresponding to the characteristic according to the output of the control program memory; and writing to the data memory based on the output of the control program memory and the parameter related to the delay time. , a control means for outputting a memory control signal for reading and addressing, and a control means for outputting an arithmetic control signal for the arithmetic means based on the output of the control program memory; By performing a predetermined operation on the signal read from the data memory in accordance with the control signal, the calculation coefficient, and the digital musical tone signal, the reverberation specified by the reverberation characteristic indicating means for the digital musical tone signal is obtained. An electronic musical instrument characterized by output with added characteristics.