JPH0157800B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a reverberant sound adding device, and more particularly to a reverberant sound adding device that generates by synthesizing reverberant sound with irregular delay time and amplitude level and regular reverberant sound. Conventionally, the BBD (Bucket Brigade) is a device that creates reverberation sound using an electronic circuit.
Many devices use analog delay elements such as devices (Devices) and CCDs (Charge Coupled Devices), but the circuit configuration in this case is to connect its own delayed signal output to the input side, as shown in Figure 1, a typical example. Some devices have a feedback loop FBL that feeds back to the input musical tone signal and the feedback signal, and a signal obtained by adding the input musical tone signal and the feedback signal is output after being delayed by the time DT using a delay circuit DC made of a BBD or the like. According to the circuit having such a configuration, as shown in FIG. 2, reverberant sound exhibiting a regular impulse response determined by the delay time DT of the delay circuit DC and the gain g of the feedback loop FBL can be obtained. However, when we analyze the actual reverberant sound in concert halls, etc., we find that the initial reflections reflected from walls and floors have irregular amplitude levels and delay times, as shown in the impulse response characteristic diagram in Figure 3.
ECH appears first, followed by reverberant sound RV with regular amplitude level and reverberation time. Therefore, with the configuration as shown in FIG. 1, it is not possible to generate natural reverberant sound such as that obtained in a concert hall or the like. Therefore, as shown in FIG. 4, after connecting a plurality of delay circuits DC ₁ to DC _o in series with randomly set delay times, the delayed signal level of each delay circuit DC ₁ to DC _o is controlled by a level control circuit. Controlled independently by GC ₁ to GC _o , these are synthesized by a synthesis circuit CC to produce early reflections that exhibit the impulse response characteristics shown in Figure 3.
There are some that generate ECH and reverberant sound RV. However, in order to generate natural reverberant sound with the configuration shown in Figure 4, it is necessary to provide a large number of delay circuits, which has the disadvantage of increasing the scale of the device and being less economical. Ta. The present invention was made in view of the drawbacks of the conventional reverberation sound adding devices described above, and its purpose is to provide a reverberation sound adding device that can generate natural reverberation sound with a small-scale and economical configuration. It's about doing. For this purpose, the reverberation sound adding device according to the present invention is
a first delay circuit that outputs a plurality of delayed musical tone signals delayed by different delay times from the input musical tone signal; a level control circuit that independently controls and outputs the levels of the plurality of delayed musical tone signals; and an input musical tone. a second delay circuit that outputs the signal with a delay longer than the plurality of delayed musical tone signals output from the first delay circuit; and a feedback loop that feeds back its own delayed signal output to the input side; a third delay circuit that outputs a signal obtained by synthesizing the output signal of the second delay circuit and its own delayed signal output at a predetermined ratio, after delaying the signal by a predetermined delay time; Combines the output signal of the delay circuit and
The synthesizer includes a synthesis circuit that outputs the synthesized signal as a reverberation signal of the input musical tone signal. Hereinafter, this invention will be explained in detail based on examples. FIG. 5 is a block diagram showing an embodiment of the reverberation sound adding device according to the present invention, FIG. 6 is a functional block diagram functionally representing the configuration of this embodiment, and FIGS. 7 and 8 are diagrams showing a digital memory. FIG. 2 is a block diagram showing the basic configuration of a delay circuit used to generate reverberation sound with a desired delay time. For convenience of explanation, we will first explain the basic configuration and operation of the delay circuit shown in FIGS. 7 and 8,
Next, the process of forming reverberant sound will be explained with reference to the functional block diagram of FIG. 6, and then the specific structure and operation of the embodiment shown in FIG. 5 will be explained. Basic configuration of a delay circuit using digital memory When the amplitude data SPD(t) of an input musical tone signal sampled sequentially at a predetermined sampling period To is sequentially stored in a digital memory as time elapses, the time (t - To read out the amplitude data SPD(t-i) stored in step i) at time t when i time has elapsed, when the sampling time is t, the address information ADR(t) must be changed during i time. The address interval ΔADR is added or subtracted as shown in the following equation (1) or (2), and the time (t
-i), and provide this address information ADR(t-i) to the address input of the digital memory. ADR (t-i) = ADR (t) + ΔADR ... (1) ADR (t-i) = ADR (t) - ΔADR ... (2) This allows the memory to be stored at time (t-i). Amplitude data SPD (t-i) can be read out with a delay of i time expressed as i=ΔADR×To (3).
That is, if the address interval ΔADR corresponding to the desired delay time i is given as delay time information, the amplitude data SPD (t-
i) can be read with a delay of i time. In this case, to obtain the address information ADR (t-i) at time (t-i) using the above equation (1), the amplitude data SPD (t) is changed from a high-order address to a low-order address as time passes. This is applied when sequentially storing the Further, the second equation is applied when the amplitude data SPD(t) is stored sequentially from a low address to a high address. Therefore, the delay circuit in this invention is a digital memory that sequentially stores amplitude data SPD(t).
DM, an address information generation circuit AG that forms read address information ADR (t-i) shown in equation (1) or equation (2) above, and generates the address interval ΔADR as delay time information DLD. A delay length data memory DDM is basically provided. FIG. 7 is a block diagram showing an example of a delay circuit based on this concept, which includes a digital memory DM, an address information generation circuit AG, a delay length data memory DDM, and a multiplier M. The digital memory DM stores amplitude data SPD sampled at a predetermined period To according to the clock pulse φ, as shown in the time chart of FIG.
(t) is stored in each address from ``0'' to ``9'' in order from the high address ``9'' to the low address ``0.'' Ru. Amplitude data in this digital memory DM
Designation of the write address and read address of SPD(t) is performed by address information generation circuit AG. In other words, the address information generation circuit
AG includes an address counter AC and an adder AD, and the write address information ADR(t), ADR(t+
1), ADR(t+2),...ADR(t+i), and also form the read address information ADR(t-i) expressed by the above equation (1), and use this as address information of the digital memory DM. Output as DM/ADR. i.e. address counter AC
counts the clock pulses φ with the period To, and uses the count value as the write address information of the amplitude data SPD(t) at the current sampling time t.
The information ADR(t) is outputted as ADR(t), and this information ADR(t) is supplied to the adder AD. On the other hand, the delay length data memory DDM transfers the time information DLD (ΔADR=i/To) corresponding to the desired delay time i to the adder AD.
feeds the other summing input of . Then, the adder AD
At the sampling time t, first performs the calculation expressed by the above equation (1) and outputs the calculated value as the read address information ADR (t-i) of the amplitude data SPD (t-i) from i time ago. , and then outputs the output information ADR(t) of the address counter AC as is and the write address information ADR(t) of the amplitude data SPD(t) at the current time t. As a result, from the digital memory DM,
At time t, amplitude data SPD (t-i) stored at time (t-i) i hours ago is read out, and amplitude data SPD at current time t is read out.
(t) is stored at the address specified by address information ADR(t). Amplitude data SPD (t-i) read out from digital memory DM with a delay of i time in this way
is the coefficient K for amplitude level control in the multiplier M
is multiplied and the level is controlled. The level-controlled amplitude data K·SPD(ti) is then converted into an address signal by a DA converter (not shown). Such operations are performed at each sampling time. As a result, it is possible to generate reverberant sound delayed by i hours from the input musical tone. In this case, 1
If a plurality of different delay time information DLDs are sequentially provided in a time-sharing manner at one sampling time, information regarding a plurality of reverberant sounds having different delay times can be extracted within the same sampling time. Therefore, in the embodiment of the present invention, the delay circuit shown in FIG. Used to shape sound. FIG. 8 is a block diagram showing another example of the delay circuit, in which the address counter AC of the address information generation circuit AG is constructed with a preset type down counter. Then, by presetting delay time information DLD corresponding to a desired delay time i for address counter AC and performing a down-count operation from this preset value (DLD), address information ADR (t ), ADR(t+1),...
The repetition period of ADR (t+i) is delay time information
The amplitude data SPD(t) at the current time t is set to match the delay time specified by DLD.
The amplitude data SPD(t-i) stored i hours ago is read from the address where the data should be stored. In other words, when the digital memory DM is composed of 10 words as shown in Fig. 8, the maximum value of the address interval is "10", so the amplitude data SPD (t-10 ), but the desired delay time i can be read out by e.g. 6・To
In this case, the output information of address counter AC
DM/ADR 5, 4, 3, 2, 1, 0, 5,...
... 0 is repeated, and the address range used in the digital memory DM is set to the desired delay time i.
(i=6・To), and change the address to which the amplitude data SPD(t) sampled at the current time t is to be written to the amplitude data SPD(t-i) just i time ago. match the written address, and obtain the amplitude data SPD at the current time t.
The amplitude data SPD (t-i) written i hours ago is read from the address to which (t) is to be written. For this reason, in the delay circuit of FIG. 8, the output information DM of the address counter AC is
A maximum value detection circuit MXD is provided which detects that ADR changes from "0" to "9" and presets the time information DLD output from the delay length data memory DDM into the address counter AC based on this detection signal. There is. On the other hand, the delay circuit in FIG. 8 does not directly write the amplitude data SPD(t) sampled at the current time t into the digital memory DM, but returns the amplitude data SPD(t-i) from i hours ago at a predetermined rate. Then, the feedback value K・SPD(t−i) and the amplitude data SPD sampled at the current time t
(t) is written.
For this purpose, a coefficient K
A multiplier M multiplies the multiplier M and returns it to the data input side of the digital memory DM, and the output data K・SPD(t−i) of the multiplier M and the amplitude data at the current time t.
SPD (t) and the added value “SPD (t) +
An adder AD is provided which supplies "K.SPD(t-i)" to the data input of the digital memory DM. Therefore, in the delay circuit configured in this way, when the desired delay time i is 6·To,
When the output information DM/ADR of the counter AC changes from "0" to the maximum value ("9" in this example), the delay time information DLD expressed as DLD=6-1=5 is stored in the address counter AC. Preset. As a result, the address counter AC changes to 5, 4, 3, 2, 1, 0, 5, . . . (for each sampling period To) as the sampling time progresses.
Address information that changes from 0 to DM・
ADR will be output repeatedly. and,
At each sampling time, address information
The amplitude data SPD (t-i) of i hours ago stored at the address specified by DM・ADR is first read out, and then the amplitude data SPD (t-i) of i hours ago is read from the same address as this read address. i)
and the amplitude data sampled at the current time t
Data "SPD(t)+K·SPD(t-i)" obtained by adding SPD(t) at a predetermined ratio is written. Therefore, in the delay circuit configured in this way, the amplitude data at the current sampling time t
The write address of SPD(t) is the same as the read address of amplitude data SPD(t-i) from i hours ago, and the amplitude data SPD(t-i) from i hours ago is fed back, so the amplitude level It is possible to extract data related to reverberant sound whose delay time changes regularly. Therefore, in an embodiment of the invention,
The delay circuit shown in FIG. 8 is used to generate reverberant sound with regular reverberant characteristics after the initial reflected sound occurs. Note that when the amplitude data SPD is multiplied by the coefficient K, the level of the finally obtained reverberant sound data becomes higher than the original amplitude data SPD, so in reality, this reverberant sound data is stored in the attenuator. The reverberant sound is guided to the output section through the In this case, if the coefficient K is set to "-1<K<0", an attenuator is not required. Next, the process of forming reverberant sound will be explained using the functional block diagram shown in FIG. Process of Forming Reverberant Sound First, the process of forming reverberant sound in the embodiment shown in FIG. The process of forming reverberant sound in which the delay time changes regularly. Here, these early reflected sounds and reverberant sounds are formed by mutually independent delay circuit series. This allows both to be controlled completely independently of each other. In FIG. 6, the input musical tone signal is
The amplitude data SPD(t) sampled at
The signal is supplied to the early reflected sound forming section 1, which is a delay circuit series. The early reflected sound forming unit 1 utilizes the delay circuit shown in FIG. D0
i _o times (n
= 1 to 10) before 10 types of amplitude data SPD (t-
i ₁ ), SPD (t-i ₂ ), ...SPD (t-i ₁₀ ) by an arbitrary amplitude level control coefficient K _o (n=1 to 10); Multiplier M1
~M10 multiplication value output K ₁・SPD (ti ₁ ), K ₂・
Find the relaxation of SPD(t-i ₂ ),...K ₁₀・SPD(t-i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o・SPD(t-i _o ), and calculate the sum ₁₀ 〓 ⁿ⁼¹ K _o・Adder that outputs SPD (t-i _o ) as the instantaneous value ECH (t) of the early reflected sound at the current time t
It consists of SUM. Multiplier M1-M1
0 and the adder SUM constitute a level control circuit. Note that the adder SUM has a built-in register RO that temporarily stores the above-mentioned total sum ₁₀ 〓 ⁿ⁼¹ K _o ·SPD (t-i _o ) until the next sampling time (t+1). In the early reflected sound forming section 1 having such a configuration, the amplitude data SPD(t) of the input musical tone sampled at the current time t is written to the address corresponding to the current time t among the 2048 word storage addresses of the memory D0. be included. Next, the register R0 in the adder SUM stores the total sum ₁₀ 〓 ⁿ⁼¹ K _o・SPD (t−1−i _o ) at the previous sampling time (t−1), so this register R0 The contents of will be reset. Next, 10 types of amplitude data before i _o time
Among SPD (t-i ₁ ) to SPD (t-i ₁₀ ), delay time
In order to read the amplitude data SPD (t-i ₁ ) of i ₁ from the memory D0, the address of the memory D0 corresponding to the delay time _{i 1} is specified, and the amplitude data SPD (t −i ₁ ) is read. In this case, i ₁ hour ago amplitude data SPD
The address for reading (t-i ₁ ) is the address mentioned above.
It is determined by equation (1). The amplitude data SPD(t-i ₁ ) of the delay time i ₁ thus read out is input to the multiplier M1, and the first reflected sound of the delay time i ₁ is inputted to the multiplier M1.
Multiplied by coefficient K ₁ for amplitude level control corresponding to ECH ₁ . And the multiplication value K ₁・SPD(t−i ₁ )
is input to the adder SUM and added to the current value of register R0, and the added value is stored again in register R0. In this case, the contents of register R0 are reset immediately after writing the amplitude data SPD(t) at current time t, so at this time register R0 is
The content written to is data K ₁ ·SPD (t−i ₁ ). In this way, the amplitude data SPD with delay time i ₁
(When the readout process and level control process for t-i ₁ are completed, that is, when the process regarding the first reflected sound ECH ₁ is completed, the second reflected sound with delay time i ₂ is
The reading processing and level control processing of the amplitude data SPD (t-i ₂ ) regarding ECH ₂ are performed in the same manner as the processing for forming the first reflected sound ECH ₁ . As a result, register R0 in adder SUM contains the first reflected sound.
Data regarding ECH ₁ K ₁ SPD (t-i ₂ ) and the second
Data regarding reflected sound ECH ₂ K ₂ SPD (ti ₂ )
The added value “K ₁・SPD(t−i ₁ )+K ₂・SPD(t−
i ₂ )" is stored. Such processing is similarly performed for the third reflected sound _ECH3 to the tenth reflected sound _ECH10 . As a result, the amplitude data _K1 ·SPD(t- _i1 ) regarding the first reflected sound _ECH1 to the tenth reflected sound _ECH10 is stored in the register R0.
The sum of ~K ₁₀ · SPD (t-i ₁₀ ) ₁₀ 〓 ⁿ⁼¹ K _o ·SPD (t-i _o ) is stored. Then, this total sum ₁₀ 〓 ⁿ⁼¹ K _o・SPD (t−i _o ) is the instantaneous value ECH (t) of the early reflected sound consisting of the first reflected sound ECH ₁ to the 10th reflected sound ECH ₁₀ , and the switch circuit SW is output via As shown in Table 1 below, the switch circuit SW selects and outputs the output of the register R0 during the initial reflection sound formation processing time Ta within one sampling period To, and outputs the output of the register R0 at a time Tb after the initial reflection sound formation processing.
In this case, the output of the second delay circuit series is selectively output.

[Table] The information data ECH(t) selectively output by this switch circuit SW is converted into an analog signal by a DA converter (not shown) and then applied to a speaker, where it is produced as an early reflection sound for the input musical tone. . Therefore, the first reflected sound ECH ₁ to the 10th reflected sound ECH ₁₀
By varying the delay time i _o and the coefficient K _o for amplitude level control, it is possible to obtain an early reflected sound whose amplitude level and delay time randomly change as shown in FIG. 10. Here, the sampling period To of the input musical tone is
When the setting is 0.04ms (25KHz), when reading the amplitude data SPD (t-1626) stored at an address 1626 words away from the write address ADR (t) of the amplitude data SPD (t) at the current time t. , the delay time i is i=1626×0.04≒65ms, and the early reflection sound is delayed by about 65ms from the input musical tone.
Can generate ECH _o . On the other hand, the amplitude data SPD(t) obtained by sampling the input musical tone at a predetermined period To is also supplied to the second delay circuit series that forms the reverberant sound after the initial reflected sound is generated. This second delay circuit series is provided separately from the delay memory D0, and the amplitude data SPD(t)
A delay memory D10 (corresponding to the third delay circuit) delays j times and supplies the signal to the bandpass filter BPF, and amplitude data for delay time j supplied from this memory D10 (corresponding to the second delay circuit)
A digital band-pass filter BPF consisting of a low-pass filter LPF and a high-pass filter HPF that pass only a predetermined frequency band component of SPD (t-j), and the band-pass filter BPF.
A first reverberation sound forming section 2 having a comb-type filter configuration forms reverberation sound data RVD ¹ with a coarse delay time interval based on the amplitude data SPD (t-j) that has passed through the reverberation sound data RVD ¹ ; and a second reverberation sound forming section 3 having an all-pass filter configuration that forms reverberation sound data RVD ² with close intervals. In such a configuration, the amplitude data SPD(t) sampled at the current time t is stored in the memory D1.
Of the 2048 word storage addresses at 0, the address ADR(t) corresponding to the current time t is written.
Next, the amplitude data SPD stored in the memory D10
Of (t), data SPD from j hours ago (t-j)
In order to read out the memory D1 corresponding to the delay time j
0 address is specified, and the amplitude data SPD (t-j) sampled j hours ago from the address
is read out. In this case, the amplitude data j hours ago
The address for reading SPD(t-j) is determined by the above-mentioned equation (1), as in the case of forming the early reflection sound. The delay time j is the memory D10
It can be set arbitrarily from a value according to the size of the address of 0 to 0, and can be set completely unrelated to the setting of early reflection sound.
The delay time i ₁₀ for the reflected sound ECH ₁₀ is set slightly larger (j>i ₁₀ ). The amplitude data SPD(t-j) of the delay time j thus read from the memory D10 is input to the multiplier M11 of the low-pass filter LPF, where it is multiplied by a predetermined coefficient _K11 . and,
The multiplied value _K11・SPD(t-j) is stored in register R1
is temporarily stored. Next, one sampling time (1.
To) previously written amplitude data SPD (t-j-
1) is read and this data SPD(t-j-1)
is multiplied by a predetermined coefficient _K12 in a multiplier M12. Next, the multiplication value output _K12 of the multiplier M12
SPD(t-j-1) and the amplitude data _K11・SPD(t-
j) are added, and the added value “K ₁₂・SPD(t
−j−1)+K ₁₁ ·SPD(t−j)” is temporarily stored again in register R1 and also temporarily stored in register R2. Next, the amplitude data SPD (t-j-1) written one sampling time (1.To) before the current time t is read out from the memory SD0 again, and this data SPD (t-j-1) is Multiplyed by a predetermined coefficient _K13 in multiplier M13. Then, this multiplication value _K13・SPD(t-j-1) is the value "_K12・SPD" temporarily stored in register R2.
(t-j-1)+K ₁₁・SPD(t-j)'', and the added value K ₁₂・SPD(t-j-1) +K ₁₁・SPD(t-j) +K ₁₃・SPD(t -j-1) is again temporarily stored in register R2. Next, the value “K ₁₂・SPD” temporarily stored in register R1 is
(t-j-1)+K ₁₁・SPD(t-j)" is used in the next sampling period (t+1), so this value "K ₁₂・SPD(t-j-1)+K ₁₁・SPD(t −j)”
is written to memory SD0. By performing this operation for each sampling period, the low pass filter LPF
Amplitude data SPD (t-j) of j hours ago from which high frequency components in a predetermined band have been removed is output from register R2, and this amplitude data SPD (t-j) is sent to a high-pass filter HPF. Then, the high-pass filter HPF removes low frequency components in a predetermined band from the amplitude data SPD (t-j) of j hours ago in the same way as the low-pass filter. That is, the output data SPD (t-j) of the register R2 of the low-pass filter LPF is transmitted to the multiplier M14.
and is multiplied by a predetermined coefficient _K14 in this multiplier M14. Then, the multiplication value K ₁₄・
SPD(t-j) is temporarily stored in register R3. Then a memory with one word storage address
Amplitude data SPD (t-j-1) written one sampling time (1.To) before is read from SD1, and a predetermined coefficient is applied to this data SPD (t-j-1).
K ₁₅ is multiplied in multiplier M15. next,
Multiply value _K15・SPD(t
−j−1) is added to the amplitude data K ₁₄・SPD(t−j) from j hours ago temporarily stored in the register R3, and the added value “K ₁₄・SPD(t−j)+
_K15 ·SPD(t-j-1)'' is temporarily stored in register R3 and also temporarily stored in register R4. Next, the data SPD (t-j-
1) is read out again from the memory SD1, and this read data SPD(t-j-1) is multiplied by a predetermined coefficient _K16 in the multiplier M16. Then, this multiplication value _K16・SPD(t-j-1) is stored in register R4.
The value temporarily stored in “K ₁₄・SPD(t−j)+
K ₁₅・SPD(t−j−1)” and the added value K ₁₆・SPD(t−j−1) +K ₁₄・SPD(t−j) +K ₁₅ .SPD(t−j−1) is temporarily stored in register R4. Next, the value “K ₁₄・SPD(t
−j)+K ₁₅・SPD(t−j−1) is used in the next sampling period (t+1), so this value “K ₁₄・SPD(t−j)+K ₁₅・SPD(t−j−1) ”
is written to memory SD1. By performing such an operation every sampling period To, the register R4 of the high-pass filter HPF outputs amplitude data SPD (t-j) of j hours ago from which low frequency components in a predetermined band have been removed. Note that register R1 of the low-pass filter LPF
After writing the contents of the register to memory SD0, it is not used until the next sampling period, so
It can be shared with register R3 of high pass filter HPF. In this way, the amplitude data j hours ago from which low frequency components and high frequency components in a predetermined band are removed
SPD(tj) is input to the first reverberation sound forming section 2. The first reverberation sound forming section 2 includes three delay circuits 2A, 2B, and 2C arranged in parallel, each having a comb-type filter configuration having different delay times. 3 delay circuits 2A,
The reason why 2B and 2C are provided in parallel is that if the frequency characteristics of a delay circuit with a comb-type filter configuration were used alone, they would be wavy as shown by symbols A, B, and C in Figure 11, so this is to flatten the frequency characteristics. This is to make it more effective. That is, three delay circuits 2A, 2 with different delay times
By providing B and 2C in parallel, the overall frequency characteristics can be flattened as shown by symbol D in FIG. In this case, the degree of flattening improves as the number of parallel connection of delay circuits increases. In this embodiment, the delay time of the delay circuit 2A is set to be the longest, the delay time of the delay circuit 2B is the second longest, and the delay time of the delay circuit 2C is set to be the shortest. Each of the delay circuits 2A, 2B, and 2C has the same configuration, except for the delay time setting. Therefore, in the figure, only the numbers of multipliers, registers, and memories are shown for circuits 2B and 2C, and only delay circuit 2A is shown in detail. In the first reverberant sound forming section 2 having such a configuration, the amplitude data SPD (t-j) of j hours ago that has passed through the bandpass filter BPF is first subjected to a coefficient _K17 for amplitude level control in the multiplier M17. Multiplyed. Then, the multiplication value K ₁₇・SPD(t−
j) is temporarily stored in register R5 in multiplier M17. Next, the amplitude data written x ₁ hour ago in memory D1 with storage address of 2048 words
In order to read SPD(t-x ₁ ), the address of memory D1 corresponding to delay time x ₁ is specified. By this, the amplitude data of x ₁ hour ago is stored from memory D1.
SPD(t-x ₁ ) is read. This amplitude data SPD (t-x ₁ ) is then supplied to the adder SUM,
In this adder SUM, other memories D2 and D3
and the output data of the memories D4 to D6 and D7 to D9 of the delay circuits 2B and 2C, and are temporarily stored in the register R11 in the adder SUM. In this case, the read operation of the memories D1 to D9 is performed sequentially in time division from the memories D1 to D9, and when the read operation of the memory D1 is performed, no data is output from the other memories D2 to D9. Therefore, the content written to the register R11 in the adder SUM becomes the data SPD (t-x ₁ ) read from the memory D1. On the other hand, the amplitude data read from memory D1
SPD(t-x ₁ ) is multiplied by a coefficient K ₁₈ for amplitude level control in multiplier M18 and then fed back to the input side of memory D1. And this multiplication value K ₁₈・
SPD (t-x ₁ ) is the register R at the current time t.
Data temporarily stored in 5 K ₁₇・SPD (t-j)
The added value K ₁₇ ·SPD(tj)+K ₁₈ ·SPD(tx ₁ ) is temporarily stored in register R6. Next, the amplitude data “K ₁₇・SPD(t
−j)+K ₁₈ ·SPD(t−x ₁ )” is written to the same address as the address where the amplitude data SPD(t−x ₁ ) x ₁ hours ago was stored. After this, the contents of register R6 are reset. The reason why the contents of register R6 are reset is because this register R6 will also be used for the processing of the memory D2 system in the next stage. When the processing of the memory D1 system is completed in this way, the processing of the memory D2 system is then performed in the same manner. That is, memory D with 2048 word addresses
_Amplitude data SPD (t-
x ₂ ) For circular reading, the address of the memory D2 corresponding to the delay time x ₂ is specified. As a result, the amplitude data SPD (t-x ₂ ) sampled x ₂ hours ago is read from the memory D2. Then, this amplitude data SPD (t-x ₂ ) is added to the contents of the register R11 (the contents read from the memory D1) SPD (t-x ₁ ) in the adder SUM, and the added value "SPD (t-x ₁ )+SPD(t-x ₂ )" is register R1
1 is temporarily stored. On the other hand, the amplitude data read from memory D2
SPD (t-x ₂ ) is multiplied by a coefficient K ₁₈ for amplitude level control in multiplier M19, and then stored in memory D2.
is fed back to the input side. And its multiplication value
K ₁₉ · SPD (t-x ₂ ) is added to the value K ₁₇ · SPD (t-j) temporarily stored in register R5,
The added value “K ₁₇・SPD (t-j) + K ₁₉・SPD (t
-x ₂ )" is temporarily stored in register R6. The data stored in this register R6 “K ₁₇・SPD
(t-j)+ _K19 ·SPD(t- _x2 )'' is stored at the same address where the data SPD(t- _x2 ) x ₂ hours ago was stored. After this, register R
The contents of 6 are reset. Next, the processing of the memory D3 system is performed in the same manner as the processing of the memory D2 system. A third delay circuit is constituted by the above-mentioned memories D1, D2, and D3. Therefore, at the stage when processing of the memory systems D1 to D3 is completed, the delay time of the memory system D3 is x ₃
Then, the contents stored in register R11 are SPD(tx ₁ ) + SPD (tx ₂ ) + SPD(tx ₃ ), and the contents stored in memory D3 are K ₁₇・SPD(tj)+K ₂₀・SPD( tx ₃ ). Such processing is similarly performed in delay circuits 2B and 2C. Therefore, memories D4 and D in the delay circuit 2B
5, the delay time of each system of D6 is x ₄ , x ₅ ,
x ₆ , and the memory D7 in the delay circuit 2C,
The delay time of each system of D8 and D9 is x ₇ ,
x ₈ and x ₉ , the contents of the register R11 at the stage when all processes of the delay circuits 2A to 2C are completed are RVD ¹ = ₉ 〓 ⁿ⁼¹ SPD (t-x _o ) = SPD (t-x ₁ ) + SPD (t-x ₂ ) + SPD (t-x ₃ )
+SPD(t- _x4 )+SPD(t- _x5 ) +SPD(t- _x6 )+SPD(t- _x7 )+SPD(t- _x8 )
+SPD(t- _x9 ). As a result, following the early reflected sound, a reverberant sound is obtained in which the delay time interval is coarse and the amplitude level and delay time change regularly, as shown in FIG. Note that in FIG. 12, the reverberation sound only for the delay circuit 2A is illustrated because the time relationship is complicated. The reverberant sound data RVD ¹ with a coarse delay time interval formed as described above is input to the second reverberant sound forming section 3. The second reverberation sound forming section 3 includes delay circuits 3A, 3B having an all-pass filter configuration with flat frequency characteristics,
3C are provided in series. The reason why the three delay circuits 3A, 3B, and 3C are provided in series is to form reverberant sound data RVD 2 with a closer delay time interval than the reverberant sound data RVD ¹ obtained in the first reverberant sound forming section ² . It's for a reason. Therefore, the delay time of each delay circuit 3A, 3B, 3C in the second reverberant sound forming section 3 is set shorter than the delay time of each delay circuit 2A, 2B, 2C in the first reverberant sound forming section 2. . The delay circuits 3A, 3B, and 3C have the same configuration except for the delay time settings. Therefore, in the diagram, only the numbers of multipliers, registers, and memories are shown for delay circuits 3B and 3C, and delay circuit 3
The detailed configuration of only A is shown. First, the reverberant sound data RVD ¹ output from the second reverberant sound forming section 2 is sent to the register R12 of the delay circuit 3A.
This data RVD ¹ is sent to register R
12, the data RVD ¹ (t-y ₁ ) written y ₁ hour ago is first read into the memory MD0 having a storage address of 512 words, so a delay time is required.
y The address of memory MD0 corresponding to ₁ hour is set. As a result, data RVD ¹ (t-y ₁ ) written y ₁ hour ago is read from memory MD0. Next, this data RVD ¹ (t-y ₁ ) is given a coefficient for amplitude level control in the multiplier M30.
K ₃₀ is multiplied, and the multiplied value K ₃₀・RVD ¹ (t-y ₁ )
is fed back to the input side of memory MD0. and,
Next, this feedback data K ₃₀・RVD ¹ (t−y ₁ ) and the first
The data RVD ¹ (t) supplied from the reverberation sound forming unit 2 at the current time t are added, and the added value “RVD ¹
(t)+K ₃₀・RVD ¹ (t-y ₁ )” is register R12
is temporarily stored. Next, the address of memory MD0 corresponding to delay time y ₁ is specified again, and the memory
MD0 to y Data written ₁ hour ago RVD ¹ (t
−y ₁ ) is read out again, and its read data RVD ¹
(ty ₁ ) is temporarily stored in register R13.
Next, the data “RVD ¹ (t)+K ₃₀ ·RVD ¹ (t−y ₁ )” temporarily stored in the register R12 is multiplied by the constant K ₂₉ for amplitude level control in the multiplier M29. The multiplied value K ₂₉ {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ₁ )} is the value RVD ¹ temporarily stored in the register R13.
(t-y ₁ ), and the added value RVD ¹ (t-y ₁ ) + K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ₁ )} is temporarily stored in register R13. . Next, the data “RVD” temporarily stored in register R12 is
(t)+K ₃₀・RVD ¹ (t-y ₁ )'' from the current time t.
Since it is used at the sampling time (t+y ₁ ) delayed by y ₁ hour, the data "RVD ¹ (t)+K ₃₀・
RVD ¹ (t- _{y 1} )" is the data RVD ¹ (t-
y ₁ ) is written to the same address where it was stored. When the processing by the delay circuit 3A is completed in this way, the data stored in the register R13 is RVD ¹ (t-y ₁ ) + K ₂₉ · {RVD ¹ (t) + K ₃₀ · RVD ¹ (t-y ₁ )} The signal is sent to delay circuit 3B, and the same processing as in circuit 3A is performed in delay circuit 3B. Here, the output data of delay circuits 3A, 3B, and 3C are represented by RVD ^2A , RVD ^2B , and RVD ^2C , and circuit 3
Assuming that the delay time of circuit B is y ₂ and the delay time of circuit 3C is y ₃ , registers R13 and R of circuits 3A, 3B, and 3C are
The output data of R15 and R17 are expressed by the following equations (4) to (6). RVD ^2A = RVD ¹ (t-y ₁ ) + K ₂₉・{RVD ¹ (t) +K ₃₀・RVD ¹ (t-y ₁ )} ...(4) RVD ^2B RVD ^2A (t-y ₂ )+K ₃₁・{RVD ^2A (t) +K ₃₂・RVD ^2A (t-y ₂ )} ...(5) RVD ^2C RVD ^2B (t-y ₃ )+K ₃₃・{RVD ^2B (t) +K ₃₄・RVD ^2B (t- y ₃ )} ...(6) Then, the output data RVD ^2C of the delay circuit 3C is outputted via the switch circuit SW as data for generating reverberant sound following the initial reflected sound. Here, when the delay times of each delay circuit 3A, 3B, and 3C are set in the relationship y ₁ > y ₂ > y ₃ , reverberant sound with dense delay time intervals is formed as shown in FIG. Can be done. That is, the delay circuit 3A uses the reverberant sound data formed by the first reverberant sound forming section 2 with a coarse delay time interval.
Based on RVD ¹ , the first reverberant sound data is generated at a time interval y ₁ shorter than the delay time interval of the first reverberant sound forming unit 2.
RVD ^2A , and the delay circuit 3B performs a second delay at a time interval y ₂ shorter than the delay time interval y ₁ of the circuit 3A.
form the reverberant sound data RVD ^2B . For this reason,
As the reverberation sound formation processing in the delay circuits 3A to 3C progresses, reverberation sounds with dense delay time intervals are formed. Note that the registers R12, R14, and R16 in the delay circuits 3A, 3B, and 3C are not used until the next sampling period after the processing related to their own circuits is completed, so that they can be shared in a time-division manner. Next, the specific configuration and operation of the embodiment shown in FIG. 5 will be explained. In addition, in the following explanation,
The following description will be made assuming that the apparatus shown in FIG. 5 forms reverberation sound according to the function shown in FIG. 6 described above. Specific Configuration of the Embodiment The reverberation sound adding device of the embodiment shown in FIG. 5 is roughly divided into a storage section 10, a time information generation section 20, an address information generation section 30, and a calculation section 40. The storage section 10 corresponds to the delay digital memory DM in FIG. 8, and here is composed of a data memory 100 having a plurality of memory blocks and a latch 101. The data memory 100 uses a plurality of memory blocks to store one word (16 bits) of memory SD0 to SP15 and 512 words (one word
16 bits) memories MD0 to MD15 and 2048 word memories (one word is 16 bits) D0 to D15 are provided. And this memory SD0~SD1
5. The data to be stored in MD0 to MD15 and D0 to D15 is given from the calculation unit 40, and the storage address and read address of the data are the address information DM, which is output from the address information generation unit 30.
specified by ADR, and each memory SD0~D
The data read from the latch 15 is supplied to the arithmetic unit 40 via the latch 101. The time information generating section 20 corresponds to the delay length data memory DDM in FIG. According to the instructions, each data delay memory D0 to D15, corresponding to each of the eight types of reverberation sounds (including early reflection sounds) with different reverberation characteristics,
Delay time information regarding MD0 to MD15 DLD ^m
[n] (n: indicates the memory types D0 to D15, MD0 to MD15, m: indicates the types 1 to 8) is configured to selectively output one type. That is, as shown in FIG. 15, the delay length data memory 201 includes data delay memories D0 to D15 and MD0 to MD15.
Memory block MB (D0) corresponding to each
~MB (D15), MB (MD0) ~MB (MD15)
Each memory block MB (D0) ~
MB (MD15) has eight memory addresses "0" to "0" corresponding to the eight types of reverberant sounds mentioned above.
Each memory block MB (D0) ~
Each memory address “0” to “7” of MB (MD15)
Each has different delay time information DLD ¹ [D0]
~DLD ⁸ [D0], DLD ¹ [D1] ~ ^{DLD 8} [D1],
...DLD ¹ [D15] ~ DLD ⁸ [D15], DLD ¹
[MD0] ~ DLD ⁸ [MD0],...DLD ¹ [MD15]
~DLD ⁸ [MD15] is stored in advance. Then, 3-bit parameter instruction information PSL indicating the reverberation characteristics of the reverberant sound to be generated is supplied from the parameter instruction circuit 200 as lower address information, and is further supplied to the memories MD0 to MD15, D0 to D.
Memory number information DLn (n: 0 to 15) with a 4-bit configuration that specifies the 15 memory numbers “0 to 15〓, and memory type information DLk (n: 0 to 15) with a 2-bit configuration that specifies the memory type “D, MD, SD” ( k: D, MD,
SD) is supplied from the address information generator as upper address information, the memory blocks (MB (D0) to MB
Delay time information DLD ^m [n] stored in one of the storage addresses (“0” to “7”) specified by the information PSL among (one of (MD15))
is read out and supplied to the address information generating section 30 as information defining the delay time relationship of reverberant sound having the desired reverberation characteristic specified by the parameter specifying circuit 200. Regarding memory SD0 to SD15,
Since the delay time is fixed (1.To), delay time information for the memories SD0 to SD15 is not required. In addition, the parameter designation circuit 200 outputs, together with the parameter designation information PSL, 3-bit program selection information PGS for selecting one of the desired control programs from among the eight types of control programs for forming reverberant sounds. Ru. Next, the address information generation unit 30 generates delay time information DLD ^m [n] output from the time information generation unit 20.
Based on the program selection information PGS and the master clock pulse φo that determines the period of one step of the control program, address information DM/ADR for the data memory 100 for forming reverberant sound with desired reverberation characteristics is generated. , a program memory 300, a program counter 301, and a program decode memory 3.
02, control signal output register 303, selector 3
04, address counter 305, latch 306,
It includes a subtraction circuit 307, a maximum value detection circuit 308, and an address information output circuit 309. Eight types of control programs are stored in advance in the program memory 300 in order to form reverberant sounds with eight types of reverberation characteristics, and the parameter specifying circuit 200 determines which type of control program should be output.
It is designated by program selection information PGS starting from 0. Then, the contents of the designated control program are sequentially read out step by step by the output information PC of the program counter 301 that counts the master clock pulse φo. In this case, all processes of the early reflected sound forming section 1, bandpass filter BPF, first reverberant sound forming section 2, and second reverberating sound forming section 3 explained in FIG. 6 are completed within one sampling period (To). If the sampling frequency is 25 KHz and the frequency of the master clock pulse φo is 4.8 MHz, the number of steps in one control program is within 4800/25 = 192, and the control program contents of these 192 steps are Executed every cycle To. and,
As shown in Table 2, three types of control programs are prepared for each step: type 1, type 2, and type 3, each step consisting of 16 bits of information. The filter processing and the formation of reverberant sound are performed by appropriately combining the output order of these three types of control programs and the content of each bit information.

[Table] In this case, the one-step control program consisting of 16 bits is the information OF, ADRn, RGn, DLn,
Control signal output register 303 like ADR [Kn]
There are two types: one is output as is through the memory write control signal WR1, and the other is decoded by the program decode memory 302 and output via the control signal output register 303, such as the memory write control signal WR1. The code OPC is given from program memory 300 to program decode memory 302. Note that details of the contents of Table 2 will be described later together with an explanation of the overall operation. On the other hand, the address counter 305 is connected to delay memories D0 to D15, MD0 to
Address counter corresponding to each MD15
AC (D0) ~ AC (D15), AC (MD0) ~ AC
(MD15). Each counter AC(D0) to AC(D
15), AC(MD0) to AC(MD15) are selectively put into an operating state by memory number information DLn and memory type information DLk. Information DLn and
Address counter AC(n) (n: D0 to D15, MD0 to MD1
The count output information ADR [n] of 5) is the latch 30.
6 to the address information output circuit 309 and also to the subtraction circuit 307. In this case, the output information of address counter AC(n)
ADR [n] is memory D0 to D15, MD0 to MD
Of the 15 memories, memories D0 to D15 have an address length of 2048 words, so they are configured with 11 bits so that an address range of up to 2048 words can be specified. Note that the address counter 305 is composed of RAM. The subtraction circuit 307 receives the output content of the address counter AC(n) input via the latch 306.
Subtract “1” from ADR[n] and apply the subtracted value “ADR[n]-1” to the next sampling period (t+
It is fed back to the A side input of the selector 304 for use in step 1). At the same time, the maximum value detection circuit 308
supply to. The maximum value detection circuit 308 corresponds to the detection circuit MXD in FIG.
Information “ADR[n]” obtained by subtracting [1] from ADR[n]
-1'' has reached the maximum value (all bits are "1"), it outputs a selector control signal SLB that causes the selector 304 to select the B-side input.
In the selector 304, the output information "ADR[n]-1" of the subtraction circuit 307 is input to the A side input,
Delay length data memory 201 on B side input
The output information DLD ^m [n] is input, and its output is supplied to the data input of the address counter 305 and written to the address counter AC(n) specified by the information DLn and DLk by the write control signal WR3. (preset) configuration. Therefore, in the address counter AC(n) specified by the information DLn and DLk, under the condition that the selector control signal SLB is not generated from the maximum value detection circuit 308, the current value ADR[n] is changed every sampling period. A value "ADR[n]-1" obtained by subtracting "1" is written, and the output information ADR[n] decreases toward "0" as time passes. However, the value "ADR(n)-1"
When reaches the maximum value, the selector control signal SLB is generated from the maximum value detection circuit 308, so the delay time information DLD ^m [n] is input to the address counter AC(n) via the selector 304, and the write control signal Written by WR3. Therefore, the contents of address counter AC(n) are the selector control signal
After becoming "DLD ^m [n]" due to the occurrence of SLB, it changes sequentially toward "0" as the sampling time passes. That is, the selector 30
4. In the part consisting of the address counter 305, latch 306, subtraction circuit 307, and maximum value detection circuit 308, the delay time information DLD ^m is detected at the address counter AC(n) specified by the information DLn and DLk.
Address information ADR [n] that goes around in a cycle equal to the delay time corresponding to [n] is formed. This address information ADR[n] is supplied to the address information output circuit 309. The address information output circuit 309 is the memory SD0
~SD15, memory D0~D15, memory MD0
- Address information for reading and writing information to the MD 15 is output. This address information output circuit 309 outputs data from memory D0.
i _o Read out time-delayed information and generate early reflection sound ECH (t)
, the 11-bit address information OF• _ADRO (output from the control signal output register 303) corresponding to each delay time _io of the first reflected sound ECH ₁ to the tenth reflected sound ECH ₁₀ is used. This set of information OF,
ADRn, DLn, DLk as address information DM/ADR
Output as . In addition, when writing the amplitude data SPD(t) sampled at the current time to the memory D0, the address counter corresponding to the memory D0
The output information ADR [D0] of AC (D0) is set as low-order address information, and information DLn (=DLo) and DLk (=DL _D ) specifying memory D0 is added to the upper part thereof,
This set of information ADR [D0], DLn, and DLk is output as address information DM/ADR. In addition, when writing and reading amplitude data to and from memories SD0 to SD15, all bits of the lower address information are set to "0", and the memory SD0 is written to the upper address.
Address information by adding information DLn (=DL ₀ to DL ₁₅ ) and DLk (=DL _SD ) specifying ~SD15
Output as DM/ADR. Also, reverberation
When forming RVD ¹ and RVD ² , memory D1
Address counters AC(D1) to AC(D15) corresponding to ~D15, MD0 to MD15, respectively;
AC (MD0) to AC (MD15) output information ADR
[D1] ~ADR [D15], ADR [MD0] ~ADR
(MD15) is the lower address information, information DLn and DLk are added to the upper part, and this set of information ADR[n], DLn, DLk is the address information DM,
Output as ADR. In this case, when the information OF and ADR _o should be added to the lower part of the information DLn and DLk, a control pulse is sent from the control signal output register 303.
GP1 is output. Also information DLn and DLk
When all bits of the lower address information added to the lower part of the address should be set to "0", the control signal output register 3
Control pulse GP2 is output from 03. Note that the address information output circuit 309 outputs information
It has internal registers to temporarily store DLn and DLk. Next, the calculation unit 40 stores the memories D0 to D15,
It controls the amplitude level of data stored in MD0 to MD15 and SD0 to SD15 and data read from each memory, and includes a coefficient memory 400, a selector 401, an arithmetic circuit 402, a temporary register 403, and a latch 404. Like the delay length data memory, the coefficient memory 400 has eight memory blocks corresponding to eight types of reverberant sounds with different reverberation characteristics, and each memory block has the memory blocks necessary to form each type of reverberant sound. A set of coefficients Kn (n: 1 to 32) is stored in advance. And the parameter specification circuit 200
When the parameter specification information PSL is supplied from the control signal output register 303 and the address information ADR [Kn] specifying the coefficient Kn is supplied from the control signal output register 303, the information
Information about memory blocks specified by PSL
The coefficient Kn is read from the address specified by ADR[Kn] and is supplied to the calculation input (A) of the calculation circuit 402. In the selector 401, the amplitude data SPD(t) of the input musical tone sampled by the sample-and-hold circuit SPH is input to the A side input, the read data MRD from the storage unit 10 is input to the B side input, and the latch is input to the C side input. The output data RGD of the temporary register 403 is input through the register 404, and these input data SPD(t), MRD,
One of the RGDs is selected by the selector control signal SL1 (2-bit configuration) output from the control signal output register 303, and the arithmetic circuit 402
is supplied to the calculation input (X) of The arithmetic circuit 402 has a coefficient memory 4 at the arithmetic input (A).
The coefficient Kn read from 00 is input, and is input to the calculation input (B) through latch 04 to temporary register 4.
The output data RGD of 03 is input, and the selected output data SPD of the selector 401 is input to the calculation input (X).
(t), MRD, and RGD are input, and the calculation control signal CTL is output from the control signal output register 303.
(3-bit configuration), (Y)=(A)・(X)+(B)...(7-1) (Y)=(X)+(B)...(7-2) (Y) = (X) ... (7-3) (Y) = (B) ... (7-4) (Y) = (0) ... (7-5) Execute the calculation and calculate the calculated value (Y ) as temporary register 403, storage unit 10, output register 50
0. The temporary register 403 stores the early reflection sound.
ECH (t), the calculated value (Y) of the calculation circuit 402 in the process of forming the reverberant sounds RVD ¹ and RVD ² is temporarily stored, and the stored contents are used as register output data RGD to input the C side of the selector 401 and the calculation circuit 4
It is fed back to the operation input (B) of 02, and has 32 registers R0 to R31 specified by register designation information RGn (n: 1 to 32) of 5 bits.
Input data is written into registers R0 to R31 designated by information RGn under the control of write control signal WR1. Next, the output register 500 is connected to the arithmetic circuit 402
The instantaneous value ECH (t) of the early reflected sound obtained as the calculated value (Y) of The signal is supplied to a DA converter (DAC) 502 via a converter 501. Note that the selector control signal SL1 in the selector 401 and the calculation control signal CTL in the calculation circuit 402 are included in the operation code OPC output from the control signal output register 303. Next, the operation of the above configuration will be explained. Operation explanation a Early reflection sound formation operation When forming the early reflection sound BCH (t), (1) First, in order to write the amplitude data SPD (t) of the input musical sound sampled at the current time t to the memory D0, SL1 ;SELECT(A) CTL;(Y)=(X) The selector control signal SL1 and calculation control signal CTL with the contents shown are outputted to the control signal output register 30 as the operation code OPC.
Output from 3. Thereby, the selector 401 supplies the amplitude data SPD(t) output from the sampling hold circuit SPH to the calculation input (X) of the calculation circuit 402. Further, the arithmetic circuit 402 outputs the amplitude data SPD(t) inputted to the arithmetic input (X) as a calculated value (Y). (2) Next, after specifying the address of memory D0 corresponding to the current sampling time (t),
The output data of the arithmetic circuit 402 is placed at this address.
To write SPD(t), DLn; DLo DLk; DL _D WR4; “1” (WRITE) L3; “1” (LATCH) Memory type information DLk, write control signal WR4, latch control signal L3 is the operation code OPC, and memory number information DLn is the control signal output register 3.
Output from 03. As a result, the output information ADR [D
0] is latched in the latch 306 as lower address information for writing the amplitude data SPD(t) at the current time t. Then, this latched lower address information ADR [D0] is added with memory number information DLn (=DLo) and memory type information DLk (=DL _D ) to its upper part in the address information output circuit 309, and the amplitude with respect to memory D0 is added. It is output as write address information DM/ADR of data SPD(t). As a result, the amplitude data SPD(t) at the current time t, which is applied to the data input of the memory D0 via the arithmetic circuit 402, is written to the address corresponding to the current time t by the write control signal WR4. (3) Next, in order to clear the register R0 that stores the composite value of early reflection sounds for each sampling time, the contents indicated by RGn; R0 CTL; (Y) = 0 WR1; “1” (WRITE) are cleared. Arithmetic control signal CTL and write control signal WR1 are operation codes
As OPC, register number information RGn is also output from the control signal output register 303. As a result, "0" is written into register R0. That is, register R0 is cleared. (4) Next, in order to form the first reflected sound ECH ₁ , the memory type information of the content indicated by OF・ADRn;OF・ADR ₁ DLk;DL _D GP1;“1” L2;“1” (LATCH) DLk, control pulse GP1, and latch control signal L2 are used as the operation code OPC, and address information OF/ADRn corresponding to the delay time _i1 of the first reflected sound ECH1 is sent to the control signal _output register 3.
Output from 03. In this case, the address information output circuit 309 holds the memory number information DLn (=DLo) in step (3). As a result, the address information output circuit 30
9 is address information corresponding to delay time i ₁
OF・ADR ₁ is the lower address information, memory number information DLn (=DLo), memory type information
Amplitude data written from memory D0 to i ₁ hour ago with DLk (=DL _D ) as upper address information
Address information for reading SPD (ti ₁ )
Output as DM/ADR. This results in
Memory D0 to i Amplitude data SPD from ₁ hour ago
(t-i ₁ ) is read, and this read data
SPD(t-i ₁ ) is latched into latch 101 by latch control signal L2. (5) Next, latch 40 the current value of register R0.
4, the latch control signal L1 with the content indicated by RGn; R0 L1 ; "1" (LATCH) is output as an operation code and register number information RGn is output from the control signal output register 303. This allows register R0
The current value of is transferred to latch 404 and stored. (6) Next, the amplitude data SPD (t−i ₁ ) ₁ hour before i
is multiplied by the coefficient K ₁ for amplitude level control, and _{the instantaneous value K 1 ·} SPD (t
−i ₁ ), the select control signal SL1, shown as ADR[Kn];ADR[K ₁ ] SL1;SELECT(B) CTL;(A)・(X)+(B)](Y), is calculated. Control signal CTL serves as operation code OPC and address information for reading constants.
ADR [Kn] is the control signal output register 303
is output from. As a result, the first
The coefficient K ₁ related to the reflected sound ECH ₁ is read out and supplied to the calculation input (A) of the calculation circuit 402 . In addition, the selector 401 selects the amplitude data SPD (t-i ₁ ) of i ₁ hour ago supplied from the latch 101 to the B-side selection input, and
SPD (ti ₁ ) is supplied to the calculation input (X) of the calculation circuit 402. In addition, the arithmetic circuit 402 (Y)=(A)・(X)+(B)=K ₁・SPD(t−i ₁ )+
Perform the operation indicated by [R0]. In this case, the contents of register R0 were cleared in step (3) above, so here we will discuss the first reflected sound.
The instantaneous value K ₁ ·SPD (ti ₁ ) regarding ECH ₁ is obtained as the calculated value (Y) of the calculation circuit 402. (7) Next, the instantaneous value K ₁・SPD of the first reflected sound ECH ₁
(t-i ₁ ) is transferred to register R0 and stored, the write control signal WR1 with the content indicated by RGn=R0 WR1; “1” (WRITE) is used as the operation code ORC, and the register number information RGn is It is output from the control signal output register 303. As a result, the output data (Y) = K ₁ · SPD (ti ₁ ) of the arithmetic circuit 402 is transferred to the register R0.
written to. By completing the steps up to this point, the instantaneous value K1 _· SPD(t- _i1 ) of the first reflected sound _ECH1 is obtained in the register R0. (8) Next, 2nd reflected sound ECH ₂ ~ 10th reflected sound
Instantaneous value K ₂ · SPD (t-i ₂ ) for ECH ₁₀ ~
K ₁₀・SPD (t−i ₁₀ ) is the step (4) above
It is formed in the same manner as (7). Therefore, when the operation of step (7) regarding the 10th reflected sound ECH ₁₀ is completed, the first reflected sound is stored in the register R0.
The sum of the instantaneous values of ECH ₁ to 10th reflected sound ECH ₁₀ is obtained: ₁₀ 〓 ⁿ⁼¹ Kn×SPD (t− _io ). Then, this sum ₁₀ 〓 ⁿ⁼¹ Kn・SPD(t−i _o ) is the write control signal for the output register 500.
Written by WR2 and forwarded to attenuator 501. b Filter operation When performing filter operation (1) First, in order to read the amplitude data SPD (t-j) of j hours ago from memory D10, DLn; DL ₁₀ DLk; DL _D L3 ; “1” (LATCH) L2 ; Memory type information DLk and latch control signals L3 and L2 with the content indicated by “1” (LATCH) are used as the operation code OPC and memory number information DLn.
is output from the control signal output register 303. As a result, the output information of address counter AC (D10) corresponding to memory D10
ADR [D10] is amplitude data SPD j hours ago
(t-j) is latched into latch 306 as lower address information for reading. And this latched lower address information
ADR [D10] is the address information output circuit 3
In 09, memory number information DLn is placed above it.
(=DL ₁₀ ) and memory type information DLk (=
DL _D ) is added to D of data memory 100.
10, the amplitude data SPD(tj) is output as read address information DM/ADR. As a result, the amplitude data SPD (t-j) of j hours ago is read from the memory D10,
This read data SPD(t-j) is latched in latch 101 by latch control signal L2. (2) Next, the amplitude data SPD(t) sampled at the current time t is converted into the amplitude data SPD(t-j)
In order to write to the same address as the read address, the select control signal SL1 and calculation control signal CTL with the contents shown as SL1; SELECT(A) CTL; (Y) = (X) are sent to the control signal output register as the operation code OPC. 30
Output from 3. Thereby, the selector 401 supplies the amplitude data SPD(t) output from the sampling hold circuit SPH to the calculation input (X) of the calculation circuit 402. Further, the arithmetic circuit 402 outputs the amplitude data SPD(t) inputted to the arithmetic input (X) as a calculated value (Y). (3) Next, the amplitude data SPD(t) is stored in the memory D1.
To write to 0, the _memory type information DLk, the write control signal WR4 _, and the latch control signal L3 are As the operation code OPC and the memory number information DLn is the control signal output register 3
Output from 03. As a result, the output information of address counter AC (D10) corresponding to memory D10
ADR [D10] is the amplitude data at the current time t
It is latched in latch 306 as lower address information for writing SPD(t). And this latched lower address information
ADR [D10] is the address information output circuit 3
In 09, memory number information DLn is placed above it.
(=DL ₁₀ ) and memory type information DLk (=
DL _D ) is added to write address information of amplitude data SPD(t) to memory D10.
Output as DM/ADR. This results in
The amplitude data SPD(t) at the current time t, which is applied to the data input of the memory D10 via the arithmetic circuit 402, is written to the address corresponding to the current time t by the write control signal WR4. (4) Next, in the low pass filter LPF,
To calculate [R1] + K ₁₁ · SPD (t-j) using the contents of register R1, coefficient K ₁₁ , and amplitude data SPD (t-j) from j hours ago, and store this calculated value in register R1 again. , First, the latch control signal L1 indicated by the contents of RGn;R1 L1;“1” (LATCH) is used as the operation code ORC, and the register number information RGn is used as the control signal output register 3.
03 and the contents of register R1 are transferred to latch 404. (5) Next, to calculate K ₁₁・SPD(t−j), ADR[Kn); ADR[K ₁₁ ] SL1; SELECT(B) CTL; (Y)=(A)・(X) +(B) Selector control signal SL1 with the content indicated by
Arithmetic control signal CTL is the operation code
As ORC, address information ADR [Kn] for constant reading is control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
_K11 is read and is the calculation input to the calculation circuit 402.
(A) is supplied. Further, the selector 401 selects the amplitude data SPD (t-j) latched in the latch 101 in the previous step b-(1), and supplies it to the calculation input (X) of the calculation circuit 402. Thereby, the arithmetic circuit 402 performs the calculation (Y)=A*(X)+(B)= _K11 *SPD(t-j)+R1. In this case, the contents of register R1 were cleared at the stage when the filter processing at the previous sampling time (t-1) was completed, so in this step, _K11・SPD
(t-j) is obtained as the calculated value (Y). (6) Next, this calculated value (Y) = K ₁₁・SPD (t-
j) in the register R1, the write control signal WR1 indicated by the contents of RGn;R1 WR1;“1” (WRITE) is output as the operation code ORC, and the register number information RGn is output from the control signal output register 303. be done. As a result, the output data _K11 ·SPD(tj) of the arithmetic circuit 402 is stored in the register R1. (7) Next, in order to read the amplitude data SPD (t-j-1) of (j-1) time ago from memory SD0, DLn; DLo DLk; DL _SD GP2; “1” L2; “1” ( LATCH) Memory type information DLk, latch control signal L2, gate pulse signal GP2
is output as the operation code ORC and memory number information DLn is output from the control signal output register 303. Then, the address information output circuit 309 sets all bits of the lower address information to "0" and outputs memory number information DLn (=DLo) and memory type information in the upper order.
DLk (wDL _SD ) is added and output as address information DM/ADR for memory SD0.
As a result, the amplitude data SPD (t-j-1) of (j-1) time ago is read from the memory SD0 and latched in the latch 101. (8) Next, the contents of register R1 K ₁₁・SPD(t
-j), the coefficient _K12 , and the amplitude data SPD (t-j-1) latched in the latch 101, calculate _K12・SPD(t-j-1)+[R1], and store this calculated value in the register. In order to store it again in R1, first, the latch control signal L1 with the contents indicated by RGn;
Output from 03, contents of register R1
K ₁₁ ·SPD(t-j) is transferred to latch 404. (9) Next, in order to calculate K ₁₂・SPD (t-j-1) + [R1], ADR [Kn]; ADR [K ₁₂ ] SL1; SELECT (B) CHL; (Y) = ( The signals SL1 and STL with the contents shown by A)・(X)+(B) are used as the operation code OPC, and the address information ADR [Kn] is used as the control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
_K11 is read and is the calculation input to the calculation circuit 402.
(A) is supplied. Also, the selector 401 selects the amplitude data latched in the latch 101.
SPD (t-j-1) is selected and the arithmetic circuit 40
It is supplied to the calculation input (X) of No.2. As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)・(X)+(B)=K ₁₂・SPD(tj-1) +K ₁₁・SPD(tj) . This calculated value (Y) is then stored in registers R1 and R2 in the next step. As a result, the contents of registers R1 and R2 are as follows: [R1] = [R2] = K ₁₂・SPD(t−j−1)+
K ₁₁・SPD(t-j). (10) Next, using the contents of register R2, coefficient K ₁₃ , and amplitude data SPD (t-j-1) of (j-1) time ago stored in memory SD0,
In order to calculate _K13・SPD(t-j-1)+[R2], first, the amplitude data SPD(t-j-1) is obtained from memory SD0 in the same manner as in step b-(7) above. It is read out and latched into latch 101. (11) Next, the contents of register R2 are latched 404
In order to transfer the contents of register R2 to _K12・SPD in the same manner as in step b-(8) above,
(t−j−1)+K ₁₁ ·SPD(t−j) is transferred to latch 404. (12) Next, read out the coefficient K ₁₃ and calculate K ₁₃・SPD(t−
In order to perform the operation of j-1) + [R2], it is shown as ADR [Kn]; ADR [K ₁₃ ] SL1; SELECT (B) CTL; (Y) = (A)・(X) + (B) The content signals SL1 and CTL are used as the operation code ORC, and the address information ADR [Kn] is used as the control signal output register 3.
Output from 03. As a result, the coefficients are stored in the coefficient memory 400.
_K11 is read and is the calculation input to the calculation circuit 402.
(A) is supplied. Also, the selector 401 selects the amplitude data latched in the latch 101.
SPD (t-j-1) is selected and the arithmetic circuit 40
It is supplied to the calculation input (X) of No.2. As a result, the arithmetic circuit 402 calculates (Y)=(A)・(X)+(B) =K ₁₃・SPD(t−j−1) +K ₁₂・SPD(tj−1) +K ₁₁・SPD(tj) The calculated value (Y) is output. This calculated value (Y) is then stored in register R2 in the next step, and is supplied to the high pass filter HPF via register R2. (13) In the final step in the low-pass filter LPF, the contents of register R1 are stored in the memory SD
0, and the next sampling time (t+
1), first write the contents of register R1 “K ₁₂・SPD(t−j−1)+K ₁₁・SPD(t
-j)'' is transferred to the latch 404 in the same manner as in step b-(8) above, and then the arithmetic circuit 402 is made to perform the calculation (Y)=(B), and the calculated value ``(Y) =K ₁₂・SPD(t-j-1)+
K ₁₁・SPD(t-j) is written to memory SD0. This write operation is performed using the operation code indicated by DLn; DLo DLk; DL _SD GP2; “1” WR4; “1” (WRITE)
This is done by outputting from the ORC and memory number information DLn control signal output register 303. When the operation of the low-pass filter LPF is completed, the operation of the high-pass filter HPF is performed next, but a description of the operation of this high-pass filter HPF will be omitted. Next, the operation of forming the reverberant sound RVD ¹ with coarse delay time intervals will be explained. c Formation operation of reverberant sound RVD ¹ When forming reverberant sound RVD ¹ , (1) First, coefficient K ₁₇ is added to the stored data SPD (t-j) of register R4 of high-pass filter HPF.
Multiply the multiplication value K ₁₇・SPD(t-j)
In order to store this in register R5, the latch control signal L1 and register number information RGn with the contents indicated by RGn; -j) is transferred to latch 404. (2) Next, to calculate K ₁₇・SPD(t−j), ADR[Kn];ADR[K ₁₇ ] SL1;SELECT(C) CTL;(Y)=(A)・(X) selector control signal SL1 with the contents shown;
The arithmetic control signal CTL and the address information ADR [Kn] for reading coefficients are output from the control signal output register 303. This allows the coefficients to be saved from the coefficient memory 400.
_K17 is read out and is the calculation input to the calculation circuit 402.
(A) is supplied. In addition, the selector 401 selects the data SPD latched in the latch 404.
(tj) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)=K ₁₇ ·SPD(t−j). This calculated value (Y) is stored in register R5 in the next step. (3) Next, read the amplitude data SPD (t-x ₁ ) from memory D1 x ₁ hours ago, and use this data SPD
(t-x ₁ ) and the current value of register R11 and store the added value in register R11 again, first, DLn; DL ₁ DLk; DL _D L3 ; “1” (LATCH) L2 ; “ 1” (LATCH) Latch control signals L3 and L2 with contents indicated by
Then, memory number information DLn and memory type information DLk are output from control signal output register 303. As a result, the output information ADR [D
1] is latched in latch 306 as lower address information for reading amplitude data SPD (t-x ₁ ). This lower address information ADR [D1] is then sent to the address information output circuit 30.
In step 9, memory number information DLn and memory type information DLk are added to the higher order, and outputted to the data memory 100 as address information DM/ADR of the memory D1. As a result, the amplitude data SPD (t-x ₁ ) x ₁ hours ago is read out from the memory D1, and the latch 10
It is latched at 1. (4) Next, in order to add this read data SPD (t-x ₁ ) and the current value of register R11,
After the contents of register R11 are transferred to the latch 404, the selector control signal SL1 and calculation control signal CTL with the contents shown by SL1; SELECT (B) CTL; (Y) = (Y) + (B) are output as control signals. It is output from register 303. Then, the selector 401 selects the amplitude data SPD(t-x ₁ ) latched in the latch 101.
Select the calculation input (X) of the calculation circuit 402
supply to. As a result, the arithmetic circuit 402 outputs the arithmetic value (Y) expressed as (Y)=(X)+(B)=[R11]+SPD(t- _x1 ). In this case, the contents of the register R11 are cleared at the stage when the operation at the previous sampling time (t-1) is completed. Therefore, the calculated value (Y) in step (4) is SPD(t-
x ₁ ). Thereafter, the calculated value (Y) is transferred to and stored in register R11. (5) Next, amplitude data SPD (t
−x ₁ ) and multiply it by the coefficient K ₁₈ ,
Furthermore, in order to store the added value of the multiplied value K ₁₈ · SPD (t-x ₁ ) and the content "K ₁₇ · SPD (t-j)" of the register R5 again in the register R6, first, the above-mentioned c-(1 ), the contents of register R5 “ _K17・SPD(t-
j)” is transferred to latch 404. (6) Next, the amplitude data SPD (t-x ₁ ) latched in the latch 101 and the data "K ₁₇ · SPD (t-x 1 ) latched in the latch 404
j)'' and the coefficient K ₁₈ , (Y)=K ₁₈・SPD(t−x ₁ )+K ₁₇・SPD(t
−j), selector control signal with contents shown as ADR[Kn];ADR[K ₁₈ ] SL1;SELECT(B) CTL;(Y)=(A)・(X)+(B) SL1,
The arithmetic control signal CTL and the address information ADR [Kn] for reading coefficients are output from the control signal output register 303. This allows the coefficients to be saved from the coefficient memory 400.
_K18 is read and is the calculation input to the calculation circuit 402.
(A) is supplied. Also, the selector 401 selects the amplitude data latched in the latch 101.
SPD (t-x ₁ ) is selected and supplied to the calculation input (X) of the calculation circuit 402. As a result, the arithmetic circuit 402 outputs (Y)=(A)*(X)+(B)= _K18 *SPD(t- _x1 )+ _K17 *SPD(t-j). This calculated value (Y) is then transferred to the memory D via register R6 in the next step.
1 is written to the address corresponding to the current time t. After this, the register R6 is cleared in order to perform the processing of the memory D2 system. (7) Next, processing regarding each system of memories D2 to D9 is performed in the same manner as steps c-(3) to c-(6) described above. And memory D1~
When the processing of each system of D9 is completed, information regarding the reverberant sound RVD ¹ expressed as RVD ¹ (t)= ₉ 〓 ⁿ⁼¹ SPD (t−x ₁ ) is obtained in the register R11. Next, the operation of forming reverberant sound RVD ² with dense delay time intervals will be explained. d Formation operation of reverberant sound RVD ² When forming reverberant sound RVD ² , (1) First, to read amplitude data y ₁ hour ago RVD ¹ (t-y ₁ ) from memory MD0, DLn=DLo DLk; DL _MD L3 ; “1” (LATCH) L2 ; “1” (LATCH) Latch control signals L3, L1 with the contents indicated by
Then, memory number information DLn and memory type information DLk are output from control signal output register 303. As a result, the address information DM/ADR for the memory MD0 is formed in the address information output circuit 309 in the same manner as in step c-( ₃ ) above, and the amplitude data RVD ¹ (t-y ₁ ) is read. Then, this data RVD ¹ (t
-y ₁ ) is latched in latch 101 . (2) Next, by using the amplitude data RVD ¹ (t-y ₁ ) latched in the latch 101, the output data RVD ¹ (t) of the register R11, and the coefficient K ₃₀ , K ₃₀・RVD ¹ (t-y ₁ ) is obtained. In order to calculate +RVD ¹ (t) and store the calculated value in register R12, first, the output data RVD ¹ (t) of register R11 is transferred to latch 404, and then ADR[Kn]; ADR[K ₃₀ ] SL1; SELECT(B) CTL; Select control signal SL1 with the content shown as (Y) = (A)・(X) + (B),
Arithmetic control signal CTL and address information ADR[Kn] for reading coefficients are output from control signal output register 303. As a result, the arithmetic circuit 402 has the above-mentioned c
- Similarly to step (6), the coefficient K ₃₀ is supplied to the calculation input (A), and the data RVD ¹ (t-
y ₁ ) is supplied to the calculation input (X). As a result, the arithmetic circuit 402 outputs the calculated value (Y) of (Y)=(A)·(X)+(B)=K ₃₀ ·RVD ¹ (ty ₁ )+RVD ¹ (t). This calculated value (Y) is then stored in register R12 in the next step. (3) Next, the contents of register R12 “K ₃₀・
In order to multiply "RVD ¹ (t-y ₁ ) + RVD ¹ (t)" by the coefficient K ₂₉ , the contents of register R12 are first transferred to latch 404, and then ADR [Kn]; ADR [K ₂₉ ] SL1; SELECT (C) CTL; Selector control signal SL1 with the content shown by (Y) = (A)・(X),
The arithmetic control signal CTL and the address information ADR [Kn] for reading coefficients are output from the control signal output register 303. As a result, the calculation circuit 402 has a coefficient K ₃₀
is supplied to the calculation input (A), and data "K ₃₀ ·RVD ¹ (t-y ₁ )+RVD ¹ (t)" is supplied to the calculation input (X). As a result, the calculation circuit 402 outputs the calculation value (Y) shown as (Y)=(A)・(X)=K ₂₉・{K ₃₀・RVD ¹ (t−y ₁ )+RVD ¹ (t)} do. This calculated value (Y) is stored in register R13 in the next step. (4) Next, in order to add the contents of register R13 and the data RVD ¹ (t-y ₁ ) from y ₁ hour ago and store the added value in register R13 again, perform the steps in d-(1) above. Data from memory MD0 to y ₁ hour ago RVD ¹ (t-
y ₁ ) is read out and latched into latch 101. After this, the contents of register R13 “K ₂₉・
After {K ₃₀ · RVD ¹ (t-y ₁ ) + RVD ¹ (t)}'' is transferred to latch 404, SL1; SELECT (B) CHL; (Y) = (B) + (X) Content selector control signal SL1,
A calculation control signal CTL is output from the control signal output register 303. As a result, the arithmetic circuit 402 is expressed as (Y)=(B)+(X)= ^RVD1 (t- _y1 )+ _K29・{ _K30・^RVD1 (t- _y1 )+ ^RVD1 (t)} The calculated value (Y) is output. This calculated value (Y) is stored in the register R13 in the next step and output as reverberation sound information RVD ^2A . (5) Next, the contents of register R12 “K ₃₀・
RVD ¹ (t-y ₁ ) + RVD ¹ (t)'' is used at the sampling time (t + y ₁ ) delayed by y ₁ hour, so the contents of register R12 are written to the address corresponding to the current time t in memory MD0. . (6) After this, the reverberation sound is denser than the y ₁ hour interval.
RVD ^2B and RVD ^2C are formed in the same manner. Although a bandpass filter is provided in the embodiment shown in FIG. 5 (FIG. 6), this may be omitted if necessary. Also,
As shown in the functional block diagram of FIG.
It is also possible to divide the frequency bands into three series using an HPF, a bandpass filter BPF, and a low-pass filter LPF, and to form different reverberant sounds for each frequency band in the first reverberant sound forming section 2. This can be easily achieved by simply changing the contents of the control program. Further, in the above embodiments, the delay circuit is configured by a digital memory, but the delay circuit can be configured arbitrarily, and analog delay elements such as BBDs and CCDs may be used. As described above, the reverberation sound adding device according to the present invention independently controls the level of a plurality of delayed musical sound signals obtained by delaying an input musical sound signal by different delay times, thereby producing early reflection sound signals with irregular delay times and levels. and the second
By delaying a signal obtained by synthesizing the input musical tone signal delayed by the delay circuit and its own feedback delay signal at a predetermined ratio by a predetermined delay time, a reverberant sound signal with regular delay time and level is formed. It is a composite of signals, and with this configuration,
Early reflected sound and reverberant sound can be set completely independently and arbitrarily, and multiple early reflected sounds are formed, making the reverberation more natural and realizing various sound field environments and complex reverberation characteristics. becomes possible. Therefore, natural reverberant sound such as that obtained in a concert hall or the like can be generated with a small-scale configuration. Furthermore, if a digital memory is used as the delay circuit, the S/N ratio will not decrease even if the reverberation time is increased, and reverberant sound with good sound quality can be generated. In this case, since the reverberation time can be freely changed by changing the address interval of the digital memory, there is an advantage that reverberant sound can be simulated according to various indoor conditions and environmental conditions.

[Brief explanation of drawings]

Figure 1 is a diagram showing a typical circuit configuration of a conventional reverberation sound adding device, Figure 2 is its impulse response characteristic diagram, Figure 3 is an impulse response characteristic diagram of reverberant sound in a concert hall, etc., and Figure 4 is a diagram showing a typical circuit configuration of a conventional reverberation sound adding device. A circuit configuration diagram showing another example of a conventional reverberation sound adding device, FIG. 5 is a block diagram showing an embodiment of the reverberation sound adding device according to the present invention, and FIG. 6 is a functional diagram of the embodiment of FIG. 7 and 8 are block diagrams showing the basic configuration of the delay circuit, FIG. 9 is a time chart for explaining the operation of the delay circuit in FIG. 7, and FIG. 10 is a block diagram showing the basic configuration of the delay circuit. A characteristic diagram of the early reflected sound generated in the embodiment shown in FIG. 5, FIG. 11 is a diagram showing the frequency characteristics of a delay circuit having a comb filter configuration, and FIGS. Characteristic diagram of reverberant sound, 1st
4 is a diagram showing the structure of the data memory in the embodiment of FIG. 5, FIG. 15 is a diagram showing the structure of the delay length data memory in the embodiment of FIG. 5,
FIG. 16 is a diagram showing the structure of the address counter in the embodiment of FIG. 5, and FIG. 17 is a functional block diagram showing another embodiment of the reverberation sound adding apparatus according to the present invention. DESCRIPTION OF SYMBOLS 1...Early reflected sound forming unit, 2...First reverberant sound forming unit, 3...Second reverberant sound forming unit, BPF...Band pass filter, 10...Storage unit, 20...Time information generating unit, 30...Address information generation section, 40...
...Arithmetic section.

Claims (1)

[Scope of Claims] 1. A first delay circuit that outputs a plurality of delayed musical tone signals obtained by delaying an input musical tone signal by different delay times, and that independently controls and outputs the levels of the plurality of delayed musical tone signals. a level control circuit; a second delay circuit that outputs the input musical tone signal with a delay longer than the plurality of delayed musical tone signals output from the first delay circuit; and a feedback circuit that feeds back its own delayed signal output to the input side. a third delay circuit which has a loop and outputs a signal obtained by combining the output signal of the second delay circuit and its own delayed signal output at a predetermined ratio with a delay of a predetermined delay time; A reverberation sound adding device comprising a synthesis circuit that synthesizes the output signal and the output signal of the third delay circuit and outputs the synthesized signal as a reverberation signal of an input musical tone signal.