JPH01192134A - Manufacture of semiconductor device - Google Patents
Manufacture of semiconductor deviceInfo
- Publication number
- JPH01192134A JPH01192134A JP1592288A JP1592288A JPH01192134A JP H01192134 A JPH01192134 A JP H01192134A JP 1592288 A JP1592288 A JP 1592288A JP 1592288 A JP1592288 A JP 1592288A JP H01192134 A JPH01192134 A JP H01192134A
- Authority
- JP
- Japan
- Prior art keywords
- insulating film
- etching
- contact hole
- semiconductor device
- mask
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Landscapes
- Drying Of Semiconductors (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Weting (AREA)
Abstract
(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.
Description
【発明の詳細な説明】
〔発明の目的〕
(産業上の利用分野)
本発明は半導体装置の製造方法に関し、特に微細コンタ
クトへのテーパ形成技術に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Object of the Invention] (Industrial Application Field) The present invention relates to a method for manufacturing a semiconductor device, and particularly to a technique for forming a taper into a fine contact.
(従来の技術)
現在多層配線工程のコンタクトホール形成は、第5図に
示す様にコンタクトのパターンニングをした後、層間絶
縁膜をRIE (反応性イオンエツチング)において異
方的にエツチングし、−層目の配線と、2層目の配線の
導通をとっている。(Prior Art) Currently, contact holes are formed in a multilayer interconnection process by patterning contacts as shown in FIG. The wiring in the first layer and the wiring in the second layer are electrically connected.
ところが、この技術では、コンタクトホールが小さくな
った場合コンタクトにAQが入り込めずにAQが断切れ
する恐れがある。However, with this technique, if the contact hole becomes small, AQ may not be able to enter the contact and AQ may be cut off.
乙
このため、第4図のようにコンタクトホール等方的に絶
縁膜をEigする事によりテーパ角をっけてiの断切れ
やAl1がコンタクト底部に入り込めない事がないよう
に対策を行っている。このコンタクトホールにテーパ角
をつける方法としては、レジストをマスクにVatエツ
チングもしくはCDE(ケミカルドライエツチング)を
用いている。B For this reason, as shown in Figure 4, measures were taken to prevent the insulating film from being cut off at the taper angle and preventing Al1 from entering the bottom of the contact by etching the insulating film isotropically through the contact hole. ing. As a method for forming a taper angle in this contact hole, Vat etching or CDE (chemical dry etching) is used using a resist as a mask.
ところが微細なコンタクトになると、vatのエツチン
グ液が十分入り込めず必要なテーパ角が得られないとい
う問題が出て来る。これは、レジストがエツチング液に
対して疎水性である事が1つの原因である。このため、
コンタクトホールのようなパターンの場合、レジストの
被覆車高いためこの問題は増進される。また、コンタク
ト寸法が小さくなると、レジストパターニング時のレジ
ストスカムがコンタクト底部に残りやすくなりこの問題
が顕著に出て来る。However, when the contacts become fine, a problem arises in that the VAT etching solution cannot penetrate sufficiently and the necessary taper angle cannot be obtained. One reason for this is that the resist is hydrophobic to the etching solution. For this reason,
For patterns such as contact holes, this problem is exacerbated by the high resist coverage. Furthermore, as the contact dimensions become smaller, resist scum during resist patterning tends to remain at the bottom of the contact, making this problem more pronounced.
(発明が解決しようとする課題)
本発明は、微細なコンタクトホールに必要なテーパ角を
形成出来る半導体装置の製造方法を提供する事を目的と
する。(Problems to be Solved by the Invention) An object of the present invention is to provide a method for manufacturing a semiconductor device that can form a taper angle necessary for a fine contact hole.
(課題を解決するための手段)
本発明は、コンタクトホールとなる絶縁膜上にフレオン
系もしくはアルゴン系のガスを用いてスパッタエツチン
グする事により凹凸をつけてその絶縁膜をVatエツチ
ングにより等方的にエツチングする工程と、さらにレジ
ストをマスクに絶縁膜を異方的にエツチングする工程を
備えた事を特徴とする半導体装置の製造方法である。(Means for Solving the Problems) The present invention provides unevenness by sputter etching an insulating film to be a contact hole using a Freon-based or argon-based gas, and then makes the insulating film isotropic by Vat etching. This method of manufacturing a semiconductor device is characterized by comprising a step of etching the insulating film anisotropically using a resist as a mask.
(作 用)
この発明によれば、微細コンタクト底部に残ったレジス
トスカムはフレオンおよびアルゴンラジカルのスパッタ
エツチングにより、エツチングされさらに絶縁膜上も凹
凸が形成されているためエツチング液のぬれ性がよくな
りWetのエツチング液が十分入り込む事が出来る。(Function) According to the present invention, the resist scum remaining at the bottom of the microcontact is etched by sputter etching of freon and argon radicals, and the insulating film also has unevenness, which improves the wettability of the etching solution. Wet etching solution can penetrate sufficiently.
(実 施 例)
本発明の一実施例を第1図〜第4図を用いて説′明する
。(Embodiment) An embodiment of the present invention will be explained using FIGS. 1 to 4.
まず初めにSi基板■例えばP型の面方位10oの基板
を用意し、熱酸化膜■を形成した後筒1のAl■を例え
ば800人デポした後写真飾刻工程により第1のAff
i■のパターニングを行う0次にRIEにより第1のA
t■を選択的にエツチングしレジストを除去し、絶縁膜
に)をデポし絶縁膜に)の平坦化工程を行いコンタクト
のパターニングを行い1選択的にレジスト■を残置させ
る0次に例えばフレオン系のガスを用いてスパッタエツ
チングすればコンタクト底部に残っているレジストスカ
ム■は除去される。また露出している絶縁膜は凹凸のつ
いた表面形状0となる1次にVatのエツチング液でレ
ジスト■をマスクに絶縁膜に)をエツチングすれば絶縁
膜は等方的にエツチングされテーパ角のついた形状とな
るこの時、エツチングされる所は、凸凹のついた形状に
なっているため、エツチング液のぬれ性が良いため小さ
いコンタクトホールへも十分エツチング液が入り込む。First, a Si substrate (for example, a P-type substrate with a surface orientation of 10o) is prepared, and after depositing, for example, 800 Al parts of the rear cylinder 1 on which a thermal oxide film (2) has been formed, the first Af
The first A is patterned by 0-order RIE for patterning
selectively etching t■, removing the resist, depositing t) on the insulating film, performing a planarization process on the insulating film), patterning the contact, and selectively leaving the resist 1.0 Next, for example, freon-based The resist scum (2) remaining at the bottom of the contact can be removed by sputter etching using the gas. In addition, the exposed insulating film has an uneven surface shape of 0. If the insulating film is etched with a primary Vat etching solution using the resist (■) as a mask, the insulating film is etched isotropically and the taper angle is At this time, the area to be etched has an uneven shape, so that the etching liquid has good wettability, so that the etching liquid can sufficiently penetrate into the small contact hole.
この後レジスト■をマスクに異方的に例えば反応性イオ
ンエツチング(RIE)を用いて絶縁膜に)をエツチン
グすれば、第2図に示すようなテーパ角をもったコンタ
クトホールが形成される。Thereafter, by etching the insulating film anisotropically using, for example, reactive ion etching (RIE) using the resist (1) as a mask, a contact hole having a tapered angle as shown in FIG. 2 is formed.
次に第2のAffi■をスパッタし、写真飾刻工程によ
りパターニングした後エツチングすれば、第3図のよう
な形状を得る事が出来る。Next, by sputtering the second Affi*, patterning it by a photo engraving process, and etching it, a shape as shown in FIG. 3 can be obtained.
本発明によれば、コンタクトホールにテーパ角をつける
1letエツチングの前にエツチングする絶縁膜が凹凸
になっているため、エツチング液のぬれ性が良なりエツ
チング液が入りやすく、絶縁膜が容易にエツチングされ
る。このため微細コンタクトに十分対応できるため、高
集積化にむいている。According to the present invention, since the insulating film to be etched before the 1let etching for forming a taper angle in the contact hole has an uneven surface, the wettability of the etching solution is improved and the etching solution can easily enter the etching layer, making it easy to etch the insulating film. be done. Therefore, it is suitable for high integration because it can sufficiently handle fine contacts.
来例を示す断面図である。
図において
1・・・Si基板 2・・・熱酸化膜3・・
・第1のAM配線 4・・・絶縁膜5・・・レジス
ト ゛
6・・・凹凸のある絶縁膜表面
7・・・第2のl配線
℃ 勺It is a sectional view showing a conventional example. In the figure, 1...Si substrate 2...Thermal oxide film 3...
・First AM wiring 4...Insulating film 5...Resist ゛6...Insulating film surface with unevenness 7...Second l wiring ℃ 勺
Claims (3)
、前記第1層目の配線上に絶縁膜を堆積し平坦化する工
程と、前記絶縁膜上に感光材を塗布した後、写真飾刻工
程によりコンタクトホールをパターンニングする工程と
、前記感光材をマスクに露出した前記絶縁膜上を表面処
理した後、Wet液で前記絶縁膜の一部を等方的にエッ
チングする工程と、前記感光材をマスクに反応性イオン
エッチングによりコンタクトホールを形成する工程と、
第2層目の配線を形成する工程とを備えた事を特徴とす
る半導体装置の製造方法。(1) A step of forming a first layer of wiring on a semiconductor substrate, a step of depositing and planarizing an insulating film on the first layer of wiring, and a step of coating a photosensitive material on the insulating film. , a step of patterning a contact hole by a photo engraving process, and a step of isotropically etching a part of the insulating film with a wet solution after surface-treating the insulating film exposed by the photosensitive material as a mask. and forming a contact hole by reactive ion etching using the photosensitive material as a mask;
A method for manufacturing a semiconductor device, comprising the step of forming a second layer of wiring.
タクトホールである事を特徴とする請求項1記載の半導
体装置の製造方法。(2) The method of manufacturing a semiconductor device according to claim 1, wherein the contact hole is a contact hole of 2.0 μm or less.
際に、フレオン系ガス及びアルゴン系のガスを用いてス
パッタエッチングする事を特徴とする請求項1記載の半
導体装置の製造方法。(3) The method of manufacturing a semiconductor device according to claim 1, characterized in that when surface-treating the insulating film using the photosensitive material as a mask, sputter etching is performed using a Freon-based gas and an Argon-based gas.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63015922A JP2659980B2 (en) | 1988-01-28 | 1988-01-28 | Method for manufacturing semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP63015922A JP2659980B2 (en) | 1988-01-28 | 1988-01-28 | Method for manufacturing semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH01192134A true JPH01192134A (en) | 1989-08-02 |
| JP2659980B2 JP2659980B2 (en) | 1997-09-30 |
Family
ID=11902274
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP63015922A Expired - Fee Related JP2659980B2 (en) | 1988-01-28 | 1988-01-28 | Method for manufacturing semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP2659980B2 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591675A (en) * | 1993-12-22 | 1997-01-07 | Samsung Electronics Co., Ltd. | Interconnecting method for semiconductor device |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239011A (en) * | 1985-08-13 | 1987-02-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
-
1988
- 1988-01-28 JP JP63015922A patent/JP2659980B2/en not_active Expired - Fee Related
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6239011A (en) * | 1985-08-13 | 1987-02-20 | Mitsubishi Electric Corp | Manufacture of semiconductor device |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5591675A (en) * | 1993-12-22 | 1997-01-07 | Samsung Electronics Co., Ltd. | Interconnecting method for semiconductor device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP2659980B2 (en) | 1997-09-30 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| LAPS | Cancellation because of no payment of annual fees |