JPH01194366A - Manufacture of junction type field effect transistor - Google Patents

Abstract

PURPOSE:To obtain a junction-type FET of a short channel length by forming a side wall using a reactive ion etching, after which ions of an N-type impurity are implanted to form a gate area. CONSTITUTION:An N-type epitaxial layer 2 is formed to a thickness of 2-5mum on a P-type semiconductor substrate 1, after which an oxide film 4 of 5000Angstrom thick is formed by thermal oxidation. Next, a window 10 for forming a gate area is opened in a width of 1-4mum on a predetermined part, after which a SiO2 film 4A having a thickness of 2000Angstrom is formed thereon. Next, by reactive ion etching method, a film 4A is etched to form a side wall 4b made of an SiO2 film on the side of the window 10. Next, ions of an N-type impurity is implanted to form a gate film 3. After that, source drain areas 5A, 5B, source.drain electrodes 6A, 6B, and a gate electrode 8 are formed using a conventional art.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for manufacturing a junction field effect transistor, and more particularly to a method for manufacturing a junction field effect transistor with a short channel length.

[Conventional technology]

Conventionally, the channel portion of a junction field effect transistor has been formed as follows.

First, as shown in FIG. 3(a), an N-type epitaxial layer 2 is grown on a P-type semiconductor substrate 1 to a thickness of 2 to 5 μm, and then an oxide film 4 is grown thereon. Next, using photolithography technology, a window 10 for forming a gate region is opened in this oxide film 4, and a P-type impurity is introduced into the gate region 3A.
form.

Next, as shown in FIG. 3(b), after further oxidizing the surface, windows for forming sources and drains are formed at predetermined locations using photolithography, and N-type impurities are introduced to form sources and drains. Train regions 5A and 5B are formed.

Next, as shown in Figure 3 (C), after further oxidizing the surface, a contact window is opened at a predetermined location, and aluminum is
It is deposited to a thickness of ~3 μm and patterned to form source/drain electrodes 6A and 6B. Subsequently, a gate electrode 8 is formed on the back surface of the substrate to complete a junction field effect transistor.

At this time, channel chief! is the width of the bottom portion of the gate region 3A.

[Problem that the invention seeks to solve]

In the above-mentioned conventional method for manufacturing a junction field effect transistor, the channel length l is determined by the width of the window 10 for forming the gate region, that is, by the photolithography technique, so that the channel length l is determined by the photolithography technique. There is a problem in that it is extremely difficult to form a transistor with a long length.

An object of the present invention is to provide a method for manufacturing a junction field effect transistor with a short channel length.

[Means for solving problems]

The junction field effect transistor of the present invention includes a step of sequentially forming an opposite conductivity type epitaxial layer and a first insulating film on a -conductivity type semiconductor substrate, and a step of forming a gate region in a predetermined portion of the first insulating film. a step of forming a second insulating film on the entire surface after providing a window of forming a sidewall made of a second insulating film in the window, and then ion-implanting an opposite conductivity type impurity to form a gate region in the semiconductor substrate. .

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a semiconductor chip for explaining a first embodiment of the present invention.

First, as shown in FIG. 1(a), an N-type epitaxial layer 2 with a thickness of 2 to 5 μm is formed on a P-type semiconductor substrate 1, and then an oxide film 4 with a thickness of 5000 μm is formed by thermal oxidation. do. Next, using photolithography technology, a window 10 for forming a gate region is opened in a predetermined portion with a width of 1 to 4 μm, and then a second insulating film is formed on the window 10 with a thickness of approximately 2000 μm by CVD. i02 film 4A is formed.

Next, as shown in FIG. 1(b), the 5i02 film 4A is etched using a reactive ion etching method to form a sidewall 4B made of the 5i02 film on the side surface of the window 10. Window width 1t is 1.0)tm, 5i0
If the thickness t of the two films is 2000, the width of the window at this time is 1l-2t), which is 0.6 μm. That is,
A window for forming a gate region having a width of 1 μm or less can be easily formed. Next, N-type impurity ions are implanted to form the gate region 3. At this time, the width of the bottom surface of the gate region 3, that is, the channel length 12, is also approximately 0.6 μm.

Hereinafter, as shown in FIG. 1(c), source/drain regions 5A, 5B, source/train voltage i
By forming 6A, 6B and the gate electrode 8, a junction field effect transistor is completed.

Further, as shown in FIG. 1(a), after forming 5io24A with a thickness of 2000 on the entire surface including the window 10 for forming the gate region, N
Figure 1 (C) can also be achieved by ion implantation of type impurities.
As shown in , the channel length l! 2 is almost <! ! l 2
t), and a junction field effect transistor having a channel length of 1 μm or less can be easily formed.

FIG. 2 is a cross-sectional view of a semiconductor chip for explaining a second embodiment of the present invention, and shows a case where a gate region and source/drain regions are formed in a self-aligned manner.

First, as shown in FIG. 2 <a), an oxide film 4 is grown to a thickness of approximately 5000 nm on the N-type epitaxial layer 2 on the P-type semiconductor substrate 1, and the gate region and source/drain regions are After opening a window for region formation and then growing a thin oxide film, a nitride film 9 with a thickness of approximately 2000 nm is grown.
grow.

Next, as shown in FIG. 2(b), using the resist film 11 as a mask and using photolithography, reactive ion etching is performed only on the portion including the gate region, and the sidewall 9A is formed in the window 10 for forming the gate region. form,
Next, ions are implanted through this window to form the gate region 3.

Next, as shown in FIG. 2(c), the resist is removed and thermally oxidized to form an oxide film only on the portions where the nitride film 9 is not present.

After that, the nitride film 9 is removed and N-type impurities are introduced by ion implantation or the like to form source/drain regions 5A, 5B, and then source/train electrodes i6A, 6B are formed to complete the junction field effect transistor. let

In this second embodiment as well, the width of the window for forming the gate region is (e+2tt), so the channel length e2 can also be made 1 μm or less as in the first embodiment. 2(a), after forming a nitride film 9 and covering the area other than the window 10 for forming the gate region with a resist film 11, N is applied at high energy of 0.1 to 10 KeV. Even if the gate region 3 is formed by ion-implanting type impurities, a junction field effect transistor with a short channel length e2 can be similarly manufactured easily.

〔Effect of the invention〕

As explained above, the present invention provides a first insulating film on a reverse conductivity type epitaxial layer with a window for forming a gate region, then a second insulating film is provided on the entire surface, and a second insulating film is formed on the second insulating film. One conductivity type impurity is ion-implanted at high energy, or one conductivity type impurity is ion-implanted after etching the second insulating film by reactive ion etching to form a sidewall on the side surface of the window. By forming the gate region, the width of the gate region can be narrowed, which has the effect of shortening the channel length.

[Brief explanation of the drawing]

FIGS. 1(a) to (c) and 2(a) to (C) are cross-sectional views of semiconductor chips for explaining the first and second embodiments of the present invention, and FIG. 3(a) -(c) are cross-sectional views of a semiconductor chip for explaining a conventional method of manufacturing a junction field effect transistor. 1... P-type semiconductor substrate, 2... N-type epitaxial layer, 3, 3A... gate region, 4... oxide film, 4A
...SiO□ film, 4B...side wall, 5A,
5B... Source/train region, 6A, 6B... Source/drain electrode, 8... Gate electrode, 9... Nitride film, 9A... Sidewall, 10... Window.

Claims (1)

[Claims] A process of sequentially forming an opposite conductivity type epitaxial layer and a first insulating film on a semiconductor substrate of one conductivity type, and providing a window for forming a gate region in a predetermined portion of the first insulating film, and then forming a second insulating film over the entire surface. forming an insulating film on the window, and ion-implanting one conductivity type impurity from above the second insulating film with high energy, or etching the second insulating film by a reactive ion etching method to form a second insulating film in the window. 2. A method for manufacturing a junction field effect transistor, comprising the step of forming a sidewall made of an insulating film as described in step 2, and then ion-implanting an opposite conductivity type impurity to form a gate region in the semiconductor substrate.