JPH01201928A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPH01201928A
JPH01201928A JP63025789A JP2578988A JPH01201928A JP H01201928 A JPH01201928 A JP H01201928A JP 63025789 A JP63025789 A JP 63025789A JP 2578988 A JP2578988 A JP 2578988A JP H01201928 A JPH01201928 A JP H01201928A
Authority
JP
Japan
Prior art keywords
circuit pattern
semiconductor chip
chip
semiconductor device
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP63025789A
Other languages
Japanese (ja)
Inventor
Hiroshi Takeshita
竹下 博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP63025789A priority Critical patent/JPH01201928A/en
Publication of JPH01201928A publication Critical patent/JPH01201928A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
    • HELECTRICITY
    • H10SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10WGENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00Package configurations
    • H10W90/701Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Wire Bonding (AREA)

Abstract

PURPOSE:To keep a pattern from being damaged and miniaturize the whole body of a device, by causing a semiconductor chip housed in a case to be composed of: a circuit pattern; electrodes which are mounted at the side opposite to the circuit pattern; and conductive parts which are connected to the circuit pattern, thereby mounting the conductive parts in through holes which penetrate into the semiconductor chip through an insulation layer. CONSTITUTION:Electrodes 12 and a circuit pattern hold each position at the side opposite each other on the faces of a chip and through holes 14 are provided by dry etching in a semiconductor chip 11 where transistors are formed in advance on the one side face of the chip. Then, an insulation layer 15 is formed by thermal oxidation and the like in the through holes 14 and further, conductive parts 13 are provided by a vaporization process or a spatter process on the insulation layer 15.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、ケース内に収納された半導体チップを備えた
半導体装置に関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a semiconductor device including a semiconductor chip housed in a case.

〔従来の技術〕[Conventional technology]

従来、この種の半導体装置は第2図に示すように構成さ
れている。これを同図に基づいて説明すると、同図にお
いて、符号1で示すものはケース2内に収納され一例の
面に回路パターン(図示せず)を有する半導体チップ、
3はこの半導体チップ1の電極4にワイヤ5を介して接
続され前記ケース2外にその一部が露呈するリードであ
る。また、6は前記ケース2の開口部を閉塞するキャッ
プである。
Conventionally, this type of semiconductor device has been constructed as shown in FIG. To explain this based on the same figure, in the same figure, what is indicated by reference numeral 1 is a semiconductor chip that is housed in a case 2 and has a circuit pattern (not shown) on one surface;
A lead 3 is connected to the electrode 4 of the semiconductor chip 1 via a wire 5, and a portion thereof is exposed outside the case 2. Further, 6 is a cap that closes the opening of the case 2.

このように構成された半導体装置を組み立てるには、ケ
ース2内に電極4が上方に位置するように半導体チップ
1を収納し、この半導体チップ1の電極4とリード3を
接続した後、キャップ6によってケース2の開口部を閉
塞することにより行う。
To assemble the semiconductor device configured in this way, the semiconductor chip 1 is housed in the case 2 so that the electrodes 4 are positioned upward, the electrodes 4 of the semiconductor chip 1 are connected to the leads 3, and then the cap 6 is This is done by closing the opening of the case 2.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

とごろで、従来の半導体装置においては、半導体装ノブ
1の一側に回路パターン(図示せず)と電極4を設けた
ものであるため、近年の高集積化に伴い電極4の個数が
増加すると、チップの外形寸法を大きくする必要が生じ
、装置が大型化するという問題があった。そこで、電極
4の外形寸法を小さくすることが考えられるが、この場
合ワイヤボンディング時にワイヤ5が所定の接続位置と
回路パターンに跨がって接続されることになり、回路パ
ターンが損傷するという不都合があった。
In conventional semiconductor devices, a circuit pattern (not shown) and electrodes 4 are provided on one side of the semiconductor knob 1, so the number of electrodes 4 has increased with the recent trend toward higher integration. Then, it becomes necessary to increase the external dimensions of the chip, resulting in a problem that the device becomes larger. Therefore, it is conceivable to reduce the external dimensions of the electrode 4, but in this case, the wire 5 would be connected across a predetermined connection position and the circuit pattern during wire bonding, which would cause damage to the circuit pattern. was there.

本発明はこのような事情に鑑みなされたもので、ワイヤ
ボンディングをする場合のパターン損傷を防止すること
ができると共に、装置全体の小型化を図ることができる
半導体装置を提供するものである。
The present invention has been made in view of the above circumstances, and it is an object to provide a semiconductor device that can prevent pattern damage during wire bonding, and can also reduce the size of the entire device.

〔課題を解決するための手段〕[Means to solve the problem]

本発明に係る半導体装置は、ケース内に収納された半導
体チップを回路バクーンと反対側に設けられた電極およ
びこの電極と回路パターンに接続された導電部をもつチ
ップによって構成し、この導電部は半導体チップを貫通
する貫通孔内に絶縁層を介して設けられているものであ
る。
In the semiconductor device according to the present invention, a semiconductor chip housed in a case is constituted by a chip having an electrode provided on the opposite side to the circuit back and a conductive part connected to the electrode and the circuit pattern, and this conductive part is It is provided in a through hole that penetrates a semiconductor chip with an insulating layer interposed therebetween.

〔作 用〕 本発明においては、電極の個数が増加しても半導体チッ
プの外形寸法を大きい寸法に設定する必要がなくなり、
またワイヤボンディングをする場合にワイヤの接続を回
路パターンと反対側で行うことができる。
[Function] In the present invention, even if the number of electrodes increases, there is no need to set the external dimensions of the semiconductor chip to large dimensions.
Furthermore, when performing wire bonding, wire connections can be made on the side opposite to the circuit pattern.

〔実施例〕〔Example〕

以下、本発明の構成等を図に示す実施例によって詳細に
説明する。第1図は本発明に係る半導体装置を示す断面
図で、同図において第2図と同一の部材については同一
の符号を付し、詳細な説明は省略する。同図において、
符号11で示すものは一方の面に回路パターン(図示せ
ず)を有する半導体チップで、前記回路パターン(図示
せず)と反対側に設げられた多数の電極12およびこれ
ら電極12と前記回路パターン(図示せず)に接続され
たアルミニウム等の導電部13を有し、前記ケース2の
内部に収納されている。この半導体装ツブ11の導電部
13はチップを貫通する貫通孔14内に絶縁層15を介
して設けられている。
EMBODIMENT OF THE INVENTION Hereinafter, the structure etc. of this invention will be explained in detail by the Example shown in the figure. FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention. In this figure, the same members as in FIG. 2 are denoted by the same reference numerals, and detailed description thereof will be omitted. In the same figure,
11 is a semiconductor chip having a circuit pattern (not shown) on one side, a number of electrodes 12 provided on the opposite side to the circuit pattern (not shown), and a connection between these electrodes 12 and the circuit. It has a conductive part 13 made of aluminum or the like connected to a pattern (not shown), and is housed inside the case 2. The conductive portion 13 of this semiconductor chip 11 is provided in a through hole 14 penetrating the chip with an insulating layer 15 interposed therebetween.

このように構成された半導体装置おいては、電極12と
回路パターン(図示せず)とが互いに反対側のチップ面
上に位置するものであるから、電極12の個数が増加し
ても半導体チップ11の外形寸法を大きい寸法に設定す
る必要がなくなり、またワイヤボンディングをする場合
にワイヤ5の接続を回路パターン(図示せず)と反対側
で行うことができる。
In the semiconductor device configured in this manner, the electrodes 12 and the circuit pattern (not shown) are located on opposite sides of the chip, so even if the number of electrodes 12 increases, the semiconductor chip It is no longer necessary to set the external dimensions of the wire 11 to a large size, and when performing wire bonding, the wire 5 can be connected on the side opposite to the circuit pattern (not shown).

次に、本発明における半導体チップ11に導電部13を
設ける方法について説明する。
Next, a method of providing the conductive portion 13 on the semiconductor chip 11 according to the present invention will be explained.

先ず、予めその一方の面にトランジスタ(図示せず)が
形成された半導体チップ11にドライエツチング法によ
って貫通孔14を設ける。次に、この貫通孔14内に熱
酸化等によって絶縁層15を形成する。そして、この絶
縁層15上に藤着法あるいはスパッタ法によって導電部
13を設ける。
First, a through hole 14 is formed by dry etching in the semiconductor chip 11 on which a transistor (not shown) has been previously formed on one surface. Next, an insulating layer 15 is formed in this through hole 14 by thermal oxidation or the like. Then, a conductive portion 13 is provided on this insulating layer 15 by a Fuji deposition method or a sputtering method.

このようにして、半導体チップIIに導電部13を設け
ることができる。
In this way, the conductive portion 13 can be provided on the semiconductor chip II.

なお、本実施例においては、半導体チップ11の配線層
が一層である場合を示したが、本発明は多層の配線層で
も可能である。
Although this embodiment shows the case where the semiconductor chip 11 has a single wiring layer, the present invention is also applicable to multilayer wiring layers.

また、本実施例においては、ワイヤボンディング方式の
半導体装置に適用する例を示したが、本発明にこれに限
定されるものではなく、フェイスダウン方式の半導体装
置に適用できることは勿論である。
Further, in this embodiment, an example is shown in which the present invention is applied to a wire bonding type semiconductor device, but the present invention is not limited thereto, and it goes without saying that the present invention can be applied to a face-down type semiconductor device.

〔発明の効果〕〔Effect of the invention〕

以上説明したように本発明によれば、ケース内に収納さ
れた半導体チップを回路パターンと反対側に設けられた
電極およびこの電極と回路パターンに接続された導電部
をもつ千ノブによって構成し、この導電部は半導体チッ
プを貫通する貫通孔内に絶縁層を介して設けられている
ので、電極の個数が増加しても半導体チップの外形寸法
を大きい寸法に設定する必要がなくなり、装置全体の小
型化を図ることができる。また、ワイヤボンディングを
する場合にワイヤの接続を回路パターンと反対側で行う
ことができるから、従来のようにワイヤホンティング時
にワイヤが所定の接続位置と回路パターンに跨がって接
続されることがなくなり、回路パターンの損傷を確実に
防止することができる。
As explained above, according to the present invention, a semiconductor chip housed in a case is constituted by a thousand knobs having an electrode provided on the opposite side to the circuit pattern and a conductive part connected to this electrode and the circuit pattern, Since this conductive part is provided in a through hole that penetrates the semiconductor chip via an insulating layer, there is no need to set the external dimensions of the semiconductor chip to large dimensions even if the number of electrodes increases. Miniaturization can be achieved. In addition, when wire bonding is performed, wires can be connected on the side opposite to the circuit pattern, so unlike conventional wire honting, the wires are connected across the predetermined connection position and the circuit pattern. Therefore, damage to the circuit pattern can be reliably prevented.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は本発明に係る半導体装置を示す断面図、第2図
は従来の半導体装置の局部を断面して示す斜視図である
。 2・・・・ケース、3・・・・リード、11・・・・半
導体チップ、12・・・・電極、13・・・・導電部、
14・・・・貫通孔、15・・・・絶縁層。
FIG. 1 is a cross-sectional view showing a semiconductor device according to the present invention, and FIG. 2 is a perspective view showing a partial cross-section of a conventional semiconductor device. 2... Case, 3... Lead, 11... Semiconductor chip, 12... Electrode, 13... Conductive part,
14...Through hole, 15...Insulating layer.

Claims (1)

【特許請求の範囲】[Claims]  ケース内に収納され一側の面に回路パターンを有する
半導体チップと、この半導体チップの電極に接続され前
記ケース外にその一部が露呈するリードとを備えた半導
体装置において、前記半導体チップを前記回路パターン
と反対側に設けられた電極およびこの電極と前記回路パ
ターンに接続された導電部をもつチップによって構成し
、この導電部は前記半導体チップを貫通する貫通孔内に
絶縁層を介して設けられていることを特徴とする半導体
装置。
In a semiconductor device including a semiconductor chip housed in a case and having a circuit pattern on one surface, and a lead connected to an electrode of the semiconductor chip and a part of which is exposed outside the case, the semiconductor chip is The chip includes an electrode provided on the opposite side of the circuit pattern and a conductive part connected to the electrode and the circuit pattern, and the conductive part is provided in a through hole penetrating the semiconductor chip via an insulating layer. A semiconductor device characterized by:
JP63025789A 1988-02-08 1988-02-08 Semiconductor device Pending JPH01201928A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP63025789A JPH01201928A (en) 1988-02-08 1988-02-08 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP63025789A JPH01201928A (en) 1988-02-08 1988-02-08 Semiconductor device

Publications (1)

Publication Number Publication Date
JPH01201928A true JPH01201928A (en) 1989-08-14

Family

ID=12175598

Family Applications (1)

Application Number Title Priority Date Filing Date
JP63025789A Pending JPH01201928A (en) 1988-02-08 1988-02-08 Semiconductor device

Country Status (1)

Country Link
JP (1) JPH01201928A (en)

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