JPH01240010A - High speed pulse generating device - Google Patents

Abstract

PURPOSE:To generate a stable high speed pulse by generating a fundamental frequency pulse of which low frequency is stable comparatively with a fundamental pulse generating means and delaying the fundamental frequency pulse for less time than the pulse cycle of the fundamental frequency pulse variously with plural delaying means. CONSTITUTION:Delaying means 21-25 are plural means to generate a pulse delayed variously from a fundamental frequency pulse generated by a fundamental pulse generating means 1 for less time than the pulse cycle of the fundamental frequency pulse. The second delaying means 22 is a circuit to delay a clock pulse delayed for a fixed time in the first delaying means 21 for a fixed quantity further and to process the delayed signal in the same way as the first delaying means 21. A superimposed means 3 is a means to superimpose the output of the fundamental pulse generating means 1 and the plural delaying means 21, 22, 23, 24 and 25. A wired OR circuit is the output terminal 4 of the wired OR circuit, and a purposing high speed pulse column is outputted from here.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to a device ζ for generating pulses.

[Prior Art] Recently, there has been a strong demand for high-speed pulses such as 10 MHz -1, QCHZ, etc., and these high-speed pulses have been generated by a combination of a high frequency generating device and an appropriate gate.

[Problems to be Solved by the Invention] However, such conventional devices for generating high-speed pulses use gallium arsenide gates or ECL gates, making them extremely expensive devices. Also, since high frequencies were directly generated, frequency stability was not high.

SUMMARY OF THE INVENTION In view of the above-mentioned problems of the conventional high-speed pulse generator, an object of the present invention is to provide a high-speed pulse generator that is inexpensive and has frequency stability.

[Means for Solving the Problems] The present invention as claimed in claim 1 provides a basic pulse generating means for generating a fundamental frequency pulse such as a crystal oscillation circuit, and a fundamental frequency pulse having a pulse period smaller than the fundamental frequency pulse. a plurality of delay means for generating pulses variously delayed by time; and a superimposition means such as a wired OR (OR) circuit for superimposing the outputs of the basic pulse generation means and the plurality of delay means; The present invention according to claim 2, characterized in that the above object is achieved by generating a high-speed pulse with a higher frequency than the frequency, is the invention according to claim 1, wherein the delay means is provided with a Schmitt trigger circuit to stabilize the time constant. , to achieve the above objectives.

[Operation] In the present invention, in the above configuration, the fundamental pulse generating means generates a stable fundamental frequency pulse of relatively low frequency, and the plurality of delay means a time smaller than the pulse period of
With various delays, the superimposing means superimposes the fundamental frequency pulse and each of the delayed pulses to produce a fast pulse at a higher frequency than the fundamental frequency.

[Examples] The present invention will be described below based on drawings showing examples thereof.

FIG. 1 is a circuit diagram showing an embodiment of a high-speed pulse generator according to the present invention.

The fundamental pulse generating means 1 is a means for generating pulses of fundamental frequency. For example, a means such as a crystal oscillation circuit which generates a relatively low frequency pulse of about IMH2 and which is highly stable is used. As shown in the figure,
The basic pulse generating means I is composed of the following circuit.The clock pulse input terminal INPUT II is 16
This is a terminal for inputting a clock pulse of ~32MH2 and a duty ratio of 50% to 50%. Phase inversion means 12
is a 74LSO4 inverter that is connected to the input terminal 11 and inverts the phase of the input signal. 13 is
JI (-flip-flop), and the output terminal of the phase inverting means 12 is connected to the input of this Bricella Q element PRE. Further, the output terminal of the phase inversion means 12 is connected to the output terminal of the phase inversion means 74 L S 04.
K-connected to the reset terminal CLR of the flip-flop. J
Schmitt trigger circuit 14 (74LS 1
4) is connected to. Furthermore, the output terminal of the Schmitt trigger circuit 14 is connected to an OR circuit 15 (74S32
) is connected to one terminal of the In addition, the Q output terminal of the JK-flip-flop 13 is connected to its OR
It is connected to the other terminal of circuit 15 (74S32). Further, the Q output terminal of the JK-flip-flop 13 is connected to one terminal of a NAND circuit 16 (74S00). In addition, the or (OR)
The output terminal of the circuit 15 is connected to the other terminal of the NAND circuit. The output terminal of the NAND circuit 16 is connected to an inverting means 17 which is a phase inverting means.
(74SO5).

The delay means 21 to 25 are a plurality of means for generating pulses that are variously delayed from the fundamental frequency pulse generated by the fundamental pulse generating means 1 by a time shorter than the pulse period of the fundamental frequency pulse. Thus, the first delay means 21 has the following configuration.

The control signal input terminal 211 (INPUT2) is a terminal to which the control No. 18 is input manually. This input terminal 211 is connected to a voltage dividing circuit 212 consisting of a resistor (R1) and a resistor (R2).

The midpoint of this voltage dividing circuit 212 is the transistor 213 (Ql
), and controls whether the transistor 213 (Ql) is conductive or non-conductive. Transistor 213 (Q
The collector of l) is connected to the phase inverting means 74LSO4,
Resistance 215 (R11) and capacitance 21 of IOP
4 (CI). This capacitance 214 is a capacity for manually delaying the clock pulse of the basic pulse generating means 1 by a predetermined time.

The connection resistor 215 is connected to a Schmitt trigger circuit 217.
(74LS 14) and capacitance 21 G (
CG). The output terminal of the Schmitt trigger circuit 218 is connected to the phase inverting means 218 and 219.
The signal is input to the preset terminal of the JK flip-flop 221 via the input terminal. This JK flip prop 2
The Q output and the Q output of 21 are the basic pulse generating means l.
Similarly to the configuration, the resistance R17, the capacitance C11,
The signal is successively transmitted to the Schmitt trigger circuit 222, the OR circuit 223, and the phase inversion means 224 and 225.

The second delay means 22 further delays the clock pulse delayed by a predetermined time in the first delay means 21 by a predetermined amount,
This circuit processes the delayed signal in the same manner as the first delay means 21.

Hereinafter, the third, fourth, and fifth delay means are also means having similar configurations.

The superimposing means 3 is a means for superimposing the outputs of the basic pulse generating means 1 and the plurality of delay means 21, 22, 23, 24, 25. For example, as shown in the figure, it is a wired OR (OR) circuit. 4 is an output terminal of the wired OR circuit, from which a target high-speed pulse train is output.

Next, the operation of the above embodiment of the present invention will be explained.

FIG. 2 is a timing chart of signals at each part of the above embodiment.

16 to 32 MHz as shown in FIG. 2(a).

A clock pulse with a duty ratio of 50%-50% is input to the clock pulse input terminal 11. The phase of the manually inputted clock pulse is inverted by the phase inverting means 12,
It is manually input to the preset terminal of the JK flip-flop 13. On the other hand, the phase-inverted signal is again input to the reset terminal of the JK flip-flop 13 through the phase inverting means. As a result, the signal output from the Q terminal of the JK flip-flop 13 rises as shown in FIG. 2 (1). In addition, the signal output from the Q terminal of the JK flip-flop 13 is as shown in FIG.
It falls as shown in d). The signal from the Q terminal is
The Schmitt trigger circuit 14 is powered via a resistor R16 and a capacitance C11. Therefore, the signal is delayed. The output from the Schmitt trigger circuit 14 is
As shown in Figure (C), it becomes a delayed square wave. The delayed square wave and the Q output of the JK flip-flop 13 are input to the OR circuit 15. Therefore, the output of the OR circuit 15 indicates that at least one of the human input signals is high (
When in the HIC (H) state, the output becomes high (HIGH) as shown in FIG. 2(e). This output is input to the NAND circuit 16.

Further, the output of the Q terminal of the JK flip-flop 13 is input to the NAND circuit 16. Therefore, only when both the human input signals are high (HIGH), as shown in Fig. 2(f)
As shown in FIG. 2, the output of the NAND circuit 16 becomes LOW. This signal is converted into a pulse by the phase inversion means 17 of the oven collector as shown in FIG. 2(g).

Next, when the control signal of the first delay means 21 is inputted to the terminal 211, the voltage dividing circuit 2
A predetermined voltage is generated at the transistor 12, and the transistor 213 becomes conductive. Therefore, the clock pulse manually generated from the basic pulse generating means 1 via the resistor R11 is delayed by a predetermined amount by the capacitance 214 (CI).

This delayed clock pulse is passed through a Schmidtdrika circuit 217 to a JK flip-flop 221.
input to the preset terminal. Thereafter, as in the case of the basic pulse generating means l, each circuit 218, 219, 220
．． 221, 222, 223, and 224 are processed in the same way, and a pulse delayed by a predetermined amount is output from the phase inversion means 225 of the oven collector.

Also, 3rd to 5th J! ! Similarly, the delay means 23, 24, 25 obtain a plurality of pulses further delayed by a predetermined amount from the phase inverting means of the oven collector.

The superimposing means 3 is arranged so that each pulse outputted from the basic pulse generating means 1 and each of the delay means 21 to 25 is
As shown in Figure (n), superimposed high-speed pulses are obtained at the output terminal 4.

Incidentally, by changing the capacitance of the capacitance 214 of the delay means, the interval between the high-speed pulses finally obtained can be freely changed.

In addition, the components of the present invention include gallium secret gate and EC.
It is also possible to use high-speed elements such as L elements.

[Effects of the Invention] As is clear from the above, the present invention utilizes a delay means to realize an inexpensive TT without using a conventional expensive gallium secret gate or ECL element.
Since an L element or the like can be used, it is possible to generate high-speed pulses that are inexpensive and have frequency stability.

In addition, by counting up this high-speed pulse train, it is possible to create lower frequency pulses, but in that case, it is also possible to create lower frequency pulses by using very high frequency pulses while maintaining frequency stability at a low cost. Since it is possible to generate low frequency pulses with high accuracy, highly accurate pulse intervals can be achieved.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram showing an embodiment of a high-speed pulse generation device according to the present invention, and FIGS. 2(a), (1)), (C),
(d), (e), (''), (g), (11),
(1), (j), (k), (m), (n)
is a timing chart showing the operation of the same embodiment. 1...Basic pulse generating means 3...Superimposing means 4...Output terminal 21-25...1st to 5th delay means Applicant Mostic Co., Ltd. IJNZ2 agent
Patent Attorney Matsu 1) Tadashi Michi

Claims (2)

[Claims] (1) A fundamental pulse generating means that generates a pulse of a fundamental frequency; a plurality of delay means that generate pulses that are variously delayed from the fundamental frequency pulse by a time smaller than the pulse period of the fundamental frequency pulse; A high-speed pulse generation device comprising a pulse generation means and a superimposition means for superimposing outputs of a plurality of delay means, and generating a high-speed pulse having a higher frequency than the fundamental frequency. (2) The high-speed pulse generation device according to claim 1, wherein the delay means includes a Schmitt trigger circuit.