JPH01273155A - Data transfer method - Google Patents

Abstract

PURPOSE:To facilitate the error detection, and also, to shorten the error processing time by comparing store data and received data after the designated time has elapsed, repeating re-store of its received data until those data coincide in the course of a write data transfer sequence of once and storing surely write data. CONSTITUTION:A write data transfer sequence is continued until store data of a data buffer (DTB) 23 coincides with write data of a data bus 32, the store of the write data is repeated to the DTB 23, and after they have coincided, the write data transfer sequence is ended. Therefore, by the write data transfer sequence of once, the write data of a CPU 1 can be stored surely in a controller (IOC) 2. Accordingly, after a transfer of a write data block has been ended, a check of a store data block is executed and an error is detected, and it becomes unnecessary to execute a transfer of the write data block again. In such a way, the error processing is facilitated, and also, the error processing time is shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data transfer method in a computer system, and in particular, to a data transfer method that allows accurate data transfer between a processing device and a control device connected via a bus. Concerning possible data transfer methods.

[Prior art]

In a computer system, when data is transferred from a processing device to a control device via a bus, the data on the bus may change instantaneously due to external noise or the like. In this case, the control device stores and stores incorrect data.

In the conventional system, for example, Japanese Patent Application Laid-Open No. 59-100927
As stated in the publication, when data is transferred between devices in order to improve data reliability, the receiving device receives data from the transmitting data bus, stores it, and then transfers the stored data to the received data. Returned by bus. Also,
The sending device creates an error check code from the returned data. Furthermore, after the transfer of the data block is completed, the error check code is checked, and if an error is detected, the data block is transferred again.

[Problem to be solved by the invention]

In the above-mentioned conventional technology, no consideration is given to facilitating error detection and shortening error processing time.

In other words, it is necessary to return the received data and retransmit the data block when an error is detected, resulting in a problem that error detection is complicated and error processing takes time.

Additionally, if external noise is applied repeatedly and the data bus is affected, the data block to be transferred will be longer, and if noise is applied during the data block transfer, the data will be lost during error handling. Block retransmission occurs.

In this case, an error is detected during retransmission of the data block, resulting in a significant increase in the number of error handling times.

There was a problem in that the error processing time took a long time.

An object of the present invention is to provide a data transfer method that can improve such problems, facilitate error detection, and shorten error processing time.

[Means to solve the problem]

In order to achieve the above object, the data transfer method of the present invention includes:
The control device includes a processing device, a control device having means (data buffer) for storing write data outputted by the processing device, and a bus connecting them. Receive write data via.

In a data transfer method that outputs a storage response signal.

The control device includes means (a comparator) for comparing the data stored in the data buffer and the data received via the data bus after a specified time has elapsed, and when the comparison result is a mismatch.

The received data is stored in the data buffer again without outputting the storage response signal, and if the comparison results match, the storage response signal is output to notify the processing device that the write data storage is complete. The control device includes means (data buffer control unit) for terminating the write data transfer sequence, and when the control device receives and stores the write data output by the processing device via the data bus, the control device transfers the stored data and the received data after a specified time has elapsed. A feature is that the write data is reliably stored by comparing and re-storing the received data during one write data transfer sequence until the data match.

[Effect]

In the present invention, a comparator compares stored data and received data after a specified time has elapsed.

Based on the comparison result, the received data is repeatedly stored again until the stored data matches the received data during one write data transfer sequence.

Therefore, write data can be reliably stored.

〔Example〕

An embodiment of the present invention will be described below with reference to the drawings.

FIG. 2 is a block diagram of a bus control system in one embodiment of the present invention.

The bus control system of this embodiment uses a processing unit (hereinafter referred to as CPU).
) 1, and a control device (hereinafter referred to as IOC) 2, which are connected by a bus 3.

This l0C2 is an address decoder (hereinafter referred to as DEC) 2 to store write data output by the CPUI.
1. Data buffer control unit (hereinafter referred to as DBC) 22.
It includes a data buffer (hereinafter referred to as DTB) 23 and a comparator (hereinafter referred to as CMP) 24.

The bus 3 also includes an address bus 31, a data bus 32 .
and a control bus 33. Note that the control bus 33 includes a write control signal (IOW) when the CPUI outputs write data, and a storage response signal (RDY) that notifies that the l0C2 has completed storing the write data.

FIG. 1 is a timing chart showing a write data transfer sequence from CPUI to 10C2 in a bus control system according to an embodiment of the present invention.

In this embodiment, when transferring write data from the CPUI to the device C2, the CPU outputs a device selection address to the address bus 31 in order to select the device C2.

As a result, the l0C2 decodes the device selection address on the address bus 31 using the DEC21.

If it matches two device addresses, l0C
2 is selected, and the selection signal (SEL) inside 10C2
becomes 1'.

Next, the CPU outputs the write data to the data bus 32 and sets the write control signal (IOW) of the control bus 33 to 1' to start the write data transfer sequence, and sends the write data to the data bus 32 for l0C2. Please let us know that you are outputting.

l0C2 sets the data buffer write signal (D B W) to 1' when the write control signal (IOW) becomes 1' while the internal selection signal (S E L) is in the state of 411. Note that this data buffer write signal is
This is a strobe when writing data is stored in the DTB 23 in step 2.

In this way, when the data buffer write signal (D B W) becomes 1', the write data on the data bus 32 is transferred to DTB.
23. However, due to the influence of external noise etc.
When the TB 23 is stored, if the write data on the data bus 32 momentarily becomes abnormal data, the stored data also becomes abnormal.

Therefore, in this embodiment, the stored data signal (DB) of the DTB 23 and the write data of the data bus 32 are transferred to the CMP 24.
are compared. If the comparison results match, the match signal (CM″POK) becomes 1′, and if they do not match, it becomes 0.
'.

If the match signal (CMPOK) is 0' after the specified time has elapsed since the received data was stored in the DTB23 by this data buffer write signal (DBW), the DBC2
2 leaves the storage response signal (DRY) at 0' and again,
With the data buffer write signal (D B W) set to 1', write data on the data bus 32 is transferred to DT as before.
Store again in B23.

Furthermore, if the match signal (CMPOK) is 1' after re-storing the received data in the DTB 23 using the data buffer write signal (DBW) and the specified time has elapsed, the DBC 22 sets the storage response signal (DRY) to 1'. , informs the CPUI that the write data storage is complete.

When the storage response signal (DRY) becomes 1', the CPUI
The write control signal (IOW) is set to 0' to end the write data transfer sequence.

In this way, the data stored in the DTB 23 is transferred to the data bus 32.
The write data transfer sequence is continued until the write data matches the write data, and the write data is repeatedly stored in the DTB 23, and after the match is reached, the write data transfer sequence is ended.

This allows the CP to be transferred in one write data transfer sequence.
UI write data can be reliably stored in l0C2.

〔Effect of the invention〕

According to the present invention, since the write data of the processing device can be reliably stored in the control device, an error is detected by checking the stored data block after the transfer of the write data block is completed.

There is no need to transfer the write data block again.

Therefore, error processing becomes easy and error processing time can be shortened.

[Brief explanation of the drawing]

FIG. 1 is a timing chart showing a write data transfer sequence from a CPU to a control device in a bus control system according to an embodiment of the present invention, and FIG. 2 is a configuration diagram of the bus control system according to an embodiment of the present invention. . 1: Processing bag [(CPU), 2: Control device (IOCL3
:Bus, 21 Near Address Decoder (DEC). 22: Data buffer control unit (DBC), 23: Data buffer (DTB), 24: Comparator (CO
MP), 31: 7 do L/X bus, 32: data bus, 33: control bus, IOW: write control signal,
RDY: Storage response signal, SEL: Selection signal, DBW:
Data buffer write signal, DB: storage data signal,
CMPOK match signal. Figure 1

Claims (1)

[Claims] 1. A processing device, a control device having means for storing write data outputted by the processing device, and a bus connecting both devices; In a data transfer method that receives write data via a data bus and outputs a storage response signal to the processing device, the control device includes data stored in the storage means and data received via the data bus. and a means for comparing the data after a designated time has elapsed, and not outputting the storage response signal when the comparison results do not match;
Store the received data in the storage means again, and if the comparison results match, output the storage response signal, notify the processing device that the write data storage is complete, and end the write data transfer sequence. The control device receives and stores the write data output by the processing device via the data bus, compares the stored data and the received data after a specified time has elapsed, and performs one write operation. A data transfer method characterized by repeatedly re-storing received data during a write data transfer sequence until both data match.