JPH0129877Y2 - - Google Patents

Description

[Detailed description of the invention] (Technical field) The present invention relates to a simplified pattern detection control circuit that detects a specific pattern of a digital transmission signal in order to efficiently control the tap coefficients of an adaptive decision feedback automatic equalizer. It is. Specifically, in a decision feedback automatic equalizer control circuit comprising a digital signal identification circuit, a digital filter for generating a correction signal, and a control circuit for controlling the tap coefficients of the digital filter, each tap coefficient is The present invention relates to a pattern detection control circuit which generates a tap coefficient control signal corresponding to a tap coefficient and also generates a specific pattern detection signal in order to update the tap coefficient on the condition that a specific pattern is detected.

(Prior art)) Figure 1 shows the AMI code string 0, ± as a specific pattern.
0, ±1, when detecting a 1,0,0 pattern
This is a conventional example of a 0,0 pattern detection control circuit.

The +1 data input signal input from terminal 1 is
The data are sequentially shifted and stored in flip-flop circuits 2 to 5 every time T. Further, the -1 data input signal inputted from the terminal 6 is sequentially shifted and stored in the flip-flop circuits 7 to 10 at intervals of time T. 11 is a flip-flop circuit 2, 3,
From each output of 4 and 5, 0, ±1, 0, 0 and 0, +1, + which violates the bipolar violation rule
A gate circuit detects each pattern of 1, 0, 0, +1, 0, +1, 12 is a flip-flop circuit 7,
From the outputs of 8, 9, and 10, 0, -1, 0, 0, and 0, which violates the bipolar violation law.
-1, -1, 0, 0, -1, 0, -1 gate circuit that detects each pattern, 17 is gate circuit 11,
This is an AND circuit for each of the 12 outputs, and this output becomes a 0, ±1, 0, 0 pattern detection signal at the terminal 18 and is sent to the coefficient update calculation circuit 23. On the other hand, a SIGN (polarity) input signal is input to the terminal 13, and this signal is sequentially shifted and stored in flip-flop circuits 14 to 16 at intervals of time T, and these outputs are the main signal ±1 and signals delayed by 1T and 2T. SIGN is exclusive OR (EX-OR))
Through circuits 19 and 20, a 1-tap coefficient control signal and a 2-tap coefficient control signal are output to terminals 21 and 22, and are input to a coefficient update calculation circuit 23. The circuit shown in Figure 1 uses three signals: +1 data input signal, -1 data input signal and SIGN signal input, so there is redundancy, and 0, ±1 from +1 data input signal and -1 data input signal. , 0, 0 (hereinafter including 0, ±1, ±1, 0, 0, ±1, 0, ±1) pattern detection must be performed using four pairs of input lines for the gate circuits 11 and 12. However, the disadvantage was that it was complicated and the circuit size became large.

(Objective of the invention) An object of the invention is to provide a pattern detection control circuit that can realize a specific pattern of a digital transmission signal with a simple circuit configuration. The present invention will be described in detail below based on examples.

(Structure of the invention) FIG. 2 is a circuit diagram showing an embodiment of the invention.
Note that the same parts shown in FIG. 1 are denoted by the same reference numerals, and the explanation thereof will be omitted. The 0/1 data input signal inputted from the terminal 25 is sequentially shifted and stored in flip-flop circuits 26 to 29 at intervals of time T. Signals 21, 22 are obtained by the same process as explained in FIG. 30 and 31 are respectively 0 and ±
1, ± ^* 1, 0 and 0, ± 1, 0, ± ^* It is a simple gate circuit that sets ±1 marked with * to 0 after 1T when one pattern is detected, and 32 is 0, ± 1, 0, This is an AND circuit for pattern detection that temporally detects the 0, 0 pattern marked with △ from the outputs of the flip-flop circuits 26 and 27 among the 0 patterns, and 33 is the 0, ±1, ±1 pattern that violates the violation rule. , 0 pattern, it is an AND circuit for pattern detection that temporally detects a pattern of ±1, 0 marked with △ from the output of the flip-flop circuit 26 and the signal 21.
4 also violates the violation law: 0, ±1, 0, ±1
This is an AND circuit for pattern detection which temporally detects a pattern of 0 and ±1 marked with Δ from the output of the flip-flop circuit 27 and the signal 22 among the patterns. Also, 3 is (x
can be either ±1 or 0) From the outputs of the flip-flop circuits 28 and 29, the time is 0 or ±1 marked with △.
This is an AND circuit for pattern detection that detects the pattern of . The output signals of the AND circuits 32 to 34 are outputted to one input of an AND circuit 37 via an OR circuit 36, and
By outputting the output signal of the circuit 35 to the other input of the AND circuit 37, a 0,±1,0,0 pattern detection signal 18 is obtained, and this signal 18 controls the gate circuits 30 and 31 described above. Further, as in the case of FIG. 1, the signals 18, 21, and 22 are input to the coefficient update calculation circuit 23, and the tap coefficients are adaptively updated only when a pattern is detected. Generally, during the training period, a repeating signal with a pattern of 0, ±, 0, 0 is sent, so the tap coefficient is updated every 4 bits of the digital signal, and during the data communication period, the tap coefficient is updated every 4 bits of the digital signal. The tap coefficient is updated when a specific pattern is detected.

In this way, in the embodiment of FIG. 2, the 0, ±1, 0, 0 pattern detection circuit is simpler than that of FIG.
It is configured with input, 3-input AND, and OR circuits without redundancy, and the number of flip-flop circuits for storing data input has been reduced by four. Like this 0,±
This has the advantage that a circuit having a 1, 0, 0 pattern detection function can be simplified and that tap coefficient control can be easily performed. In the above explanation, for simplicity, the specific patterns are AMI series 0, ±1,
Although the case where 0,0 is used has been described, it is clear that the present invention can be applied to any other code system or code sequence.

In the embodiment of FIG. 2, the gate circuits 30, 3
1 is a ±1 signal marked with △ by the pattern detection signal 18 when each pattern of 0, ±1, ±1, 0 or 0, ±1, 0, ±1 is detected by the circuits 32 to 37. When inputting to the next-stage flip-flop circuits 27 and 8, control is made so that it is input as 0.
At the time when a specific pattern of 0, ±1, 0, 0 can be detected, other patterns of 0, ±1, ±
When a pattern of 1, 0 or 0, ±1, 0, ±1 is detected, it is corrected to the correct signal sequence of 0, ±1, 0, 0, and subsequent pattern signals and coefficient control signals are corrected. will occur. That is, the gate circuits 30 and 31 prepare for the detection of the next 4-bit pattern. For example, if the current detection pattern is 0,+
1, 0, +1, and the next pattern sent is also 0, +1, 0, +1, each is a specific pattern to be detected, but the 3rd to 6th patterns in the 8-bit series 0,+1,0,
Since the pattern +1 is not the period of the specific pattern, in order to avoid detecting the pattern at such a point in time, the gate circuits 30 and 31 set the period of 0, +1, 0 every time a specific pattern is detected in preparation for the next detection. ,0
Correct the pattern.

(Effects of the invention) The present invention is very effective in pattern detection circuits for tap coefficient control of adaptive decision feedback automatic equalizers that equalize pulse transmission distortion due to reflections in digital subscriber line transmission. Since it is also simplified, it is expected that the occupied area will be reduced when converting to LSI.

[Brief explanation of drawings]

Fig. 1 is a configuration circuit diagram of a conventional 0, ±1, 0, 0 pattern detection circuit. Fig. 2 is a 0, ± 1, 0,
FIG. 2 is a configuration circuit diagram of an embodiment of a 0 pattern detection circuit. 13...SIGN input terminal, 14, 15, 16...
...Flip-flop circuit, 18...0, ±1,0,
0 pattern detection signal, 19, 20...EX-OR
Circuit, 21... 1-tap coefficient control signal, 22...
...2-tap coefficient control signal, 23...Coefficient update calculation circuit, 25...0/1 data input terminal, 26,
27, 28, 29...Flip-flop circuit, 3
0, 31...gate circuit, 32...×,×,0,
AND circuit for 0 pattern detection, 33...×,×,±
1,0 pattern detection AND circuit, 34...×,
×, 0, ±1 pattern detection AND circuit, 35...
0, ±1, ×, × AND circuit for pattern detection, 36...
...OR circuit, 37...AND circuit.

Claims (1)

[Claims for Utility Model Registration] In a decision feedback automatic equalizer control circuit comprising a digital signal identification circuit, a digital filter for generating a correction signal, and a control circuit for controlling tap coefficients of the digital filter, A first circuit 14 to 16 consisting of three stages of flip-flop circuits connected in series with the polarity signal of the signal as an input to the first stage, and each of the flip-flop circuits 1 except for the final stage.
4, 15 outputs as one input, and the output of the final stage flip-flop circuit 16 as the other input,
First and second exclusive OR circuits 19 and 20 output a tap coefficient control signal corresponding to each tap to the coefficient update calculation circuit, and a 0/1 identification signal of a digital signal is input to the first stage. A second circuit 26 to 29 consisting of four stages of flip-flops connected in series, and the output of the first stage flip-flop circuit 26 and the output of the second stage flip-flop circuit 27 of the second circuit are used as inputs, and the output becomes [0,0]. The first logic circuit 32 detects a signal pattern, and the output of the first stage flip-flop circuit 26 of the second circuit and the output of the first exclusive OR circuit 19 are input, and a signal pattern of [±1, 0] is generated. A second logic circuit 33 detects a signal pattern of [0, ±1] by inputting the output of the second stage flip-flop circuit 27 of the second circuit and the output of the second exclusive OR circuit 20. a third logic circuit 34 that detects a signal pattern of [0, ±1] using the output of the third-stage flip-flop circuit and the output of the fourth-stage flip-flop circuit of the second circuit as inputs;
a logic circuit 35; and fifth logic circuits 36 and 37 that take the AND of the OR outputs of the first to third logic circuits and the output of the fourth logic circuit, and output the result to the coefficient update calculation circuit as a specific pattern detection signal. , for each detection of the specific pattern, the first
The output signal I1 of the flip-flop circuit and the second
A pattern detection control circuit comprising means 30 and 31 for correcting an output signal of ±1 of a flip-flop circuit to a signal of 0 and inputting the corrected signal to a flip-flop circuit at the next stage.