JPH01309372A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To simplify a manufacturing process of two or more BiTr's having different hFE's by a method wherein a depth of an emitter region is controlled by referring to a balance between a thickness of a silicon layer and an opening width of an emitter window in order to form two or more emitter regions of different depths in one solid diffusion process. CONSTITUTION:Two or more emitter windows 4A, 4B of different opening widths are formed in an insulating film 3 on a semiconductor substrate 1 where, e.g., two or more p-type base regions 2A, 2B of an equal depth have been formed; an undoped silicon layer 5 of a prescribed thickness is formed on the insulating film 3 including the inside of the emitter windows. A heat treatment is executed at a high temperature for a short time; an impurity is diffused into the base regions 2A, 2B through silicon layers 5A, 5B via the emitter windows 4A, 4B from an As introduction layer 6; a first n<+> type emitter region 7A and a second n<+> type emitter region 7B are formed under the emitter windows 4A, 4B. By this setup, two or more emitter regions of different depths can be formed in one solid diffusion process.

Description

[Detailed Description of the Invention] [Summary] It is an object of the present invention to provide a manufacturing method that simplifies the process with respect to a method of manufacturing a semiconductor device, particularly a method of manufacturing a semiconductor device including a plurality of bipolar transistors having different current amplification factors. For the purpose, an emitter window is opened in the insulating film on the base region of one conductivity type,
A non-doped silicon layer is formed on the insulating film including the inside of the emitter window, and 3 layers are formed on the upper layer of the non-doped silicon layer.
! ! Impurities of opposite conductivity type are introduced into the base region by heat treatment, and the impurities are diffused into the base region through the emitter window and the non-doped region of the silicon layer, thereby forming opposite conductivity into the base region. forming a plurality of bipolar transistors on one semiconductor substrate using a step of forming a type emitter region, and changing the aperture width of the plurality of emitter windows, and changing the aperture width of the emitter window and the silicon layer. The depth of the emitter region is controlled in consideration of the thickness of the emitter window, so that a second emitter region is formed at the bottom of the emitter window with a small aperture width and is shallower than a second emitter region formed at the bottom of the emitter window with a large aperture width. It has a configuration in which one emitter region is formed.

[Industrial application field]

The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device including a plurality of bipolar transistors having different current amplification factors.

With the diversification of needs, functions, and higher performance, various requirements have arisen for the current amplification factor (hFi) of bipolar transistors. There is a demand for a semiconductor IC having a circuit configuration that is similar to the above.

However, in the semiconductor field where cost competition is intense, it is not possible to meet the above requirements by increasing the number of manufacturing steps, and there is a desire to develop a manufacturing method that does not involve an increase in manufacturing steps.

[Conventional technology]

In bipolar transistors, transistors with different hFE sizes: 1) Change the depth of the emitter and change the remaining width of the base.

■Change the emitter injection efficiency by changing the emitter concentration.

■Change the depth of the base to change the remaining width of the base.

■Changing the concentration of the base 1.Changing the injection efficiency of the emitter.

Formed by etc.

In conventional manufacturing methods, in order to achieve the above means, for example, to change the depth of the emitter or base, the impurity diffusion temperature is changed, and to change the concentration of the emitter or base, impurity ions are implanted twice. This was dealt with by increasing the number of processes.

[Problem to be solved by the invention]

However, in the conventional manufacturing method involving an increase in the number of steps described above, an increase in the number of steps and manufacturing cost is unavoidable, resulting in problems in terms of shortening delivery times and reducing costs.

Therefore, an object of the present invention is to provide a manufacturing method that simplifies the process.

[Means to solve the problem]

The above problem is to - form an emitter window in an insulating pattern on a conductivity type base region, form a non-doped silicon layer on the insulating film including the inside of the emitter window, and An opposite conductivity type impurity is selectively introduced, and by heat treatment, the opposite conductivity type impurity is diffused into the base region through the emitter window and the non-doped region of the silicon layer, thereby creating opposite four-voltage in the base region. forming a plurality of bipolar transistors on a one-half n-type substrate using a step of forming a type emitter region, and changing the aperture width of the plurality of emitter windows, and changing the aperture width of the emitter window and the silicon layer. The depth of the emitter region is controlled in consideration of the thickness of the emitter window, so that a second emitter region is formed at the bottom of the emitter window with a small aperture width and is shallower than a second emitter region formed at the bottom of the emitter window with a large aperture width. This problem is solved by a method of manufacturing a semiconductor device according to the present invention, in which one emitter region is formed.

[Function] FIGS. 1(a) to (C1) are process cross-sectional views showing the principle of the present invention.

In the method of the present invention, as shown in FIG.
) is formed on the insulating film (3) on the semiconductor substrate (1),
A plurality of emitter windows (48), (4B), etc. having different opening widths are formed, and a non-doped silicon layer (5) of a predetermined thickness is formed on the insulating film (3) including the inside of the emitter windows. In this way, the emitter window (4A) has a small opening width due to the balance between the opening widths (Wa) and (W8) of the emitter windows (4A) and (4B) and the thickness of the silicon layer (5).
The thickness of the upper silicon layer (5A) is the thickness of the silicon layer (5B) above the emitter window (4B) with a large opening width ta
becomes thicker than

The figure shows that the flowering width of the small emitter window (48) is (WA).
is typically controlled to be less than twice the grown thickness of the silicon layer (1), and the flowering width (Wll) of the large emitter window (4B) is controlled to be significantly greater than twice the grown thickness of the silicon layer (1). This is an example.

After forming the non-doped silicon layer (5) in this way, in the method of the present invention, as shown in FIG. Arsenic (As”) ion implantation (
1, I). (6) indicates the A4 group.

Then, the emitter window (48) is subjected to short-time heat treatment.
and from the top layer (6) of (4B) through the emitter window (4A), (4B) and the emitter window (48),
Impurities are diffused into the base regions (2A), (2B) through the silicon layers (58), (5B) on (4B), and the emitter windows (48), ( 4B)
a first emitter region (78) having an n-type at the bottom of the
A second emitter region (7B) is formed. At this time, as mentioned above, the thickness of the silicon layer (5A) LA is formed thick, and the emitter window (4A) with a small opening width has a long impurity diffusion distance to the base region (2A). The emitter region (78) of No. 1 is formed with a small thickness ts of the silicon layer (5B), and a deep emitter window (4B) with a large flowering width and a short diffusion distance to the base region (2B) is formed. A second emitter region (7B) is formed.

As described above, according to the method of the present invention, multiple emitter regions with different depths can be formed in a single solid-phase diffusion process, so the manufacturing process of a semiconductor device having multiple bipolar transistors having different hFEs can be greatly simplified. Be simplified.

〔Example〕

Hereinafter, the present invention will be described in Example 2 for manufacturing a semiconductor device having a plurality of bipolar transistors having different values of h and E and having an isoplanar type with a poly-Si drawn base electrode. A detailed description will be given with reference to process cross-sectional views shown in FIGS.

FIG. 2 (see 81) First, according to the usual method of forming a bipolar transistor,
On the surface of the n-type semiconductor substrate 11 serving as the collector, there is a region 12A having a width of about 3 μrn, in which a small bipolar transistor (Try) with low hyE;・For example, width 5 where the Ibora transistor (Trz) is formed
A field oxide film 13 is formed to separate and define regions 12B of about μm.

FIG. 2 (See BL) Next, a poly-Si layer having a thickness of about 0.5 μm was formed on the substrate, and conductivity was imparted to the poly-Si layer by introducing boron CB at a high concentration. After that, a silicon dioxide (Sin2) film with a thickness of approximately 2,000 yen is formed on the poly-Si drawer by thermal oxidation or CVD method, and predetermined patterning is performed by a normal method to form the first and second transistor forming regions 12A. and an insulating film 13. covering the edges of 12B.
frame-shaped first and second poly-Si-based extraction electrodes 15A extending from one side to the other and having a 5i02 film 16a on two parts;
and 15B. Here, the opening width AI that exposes the substrate surface of the first poly-Si base extraction electrode 15A is, for example, about 0.8 μm, and the second poly-Si base extraction electrode 1
The opening 'tiJWz exposing the substrate surface of 5B is formed to have a thickness of about 3 μrn.

Next, by heat treatment at about 1000°C as usual, each transistor forming area 12A is separated from each base electrode.
, 12[1] to form p° type external base regions 17A and 17B, and then base extraction electrode 1.
For example, boron (B) is introduced into the transistor formation regions 12A and 12B using 5A and 15B as masks.
equal depth of the order of 3-0.4 μm, and 5×10'8
A p-type first base region 148 and a second base region 14B having an impurity concentration of about CI11-3 are formed.

Here, 14A and 14B will be referred to as intrinsic base or internal base regions.

FIG. 2 (See C1) Next, a 02i02 film with a thickness of about 2,000 layers is formed on the above substrate by CVD method, and base extraction voltages ff115A and 15A are formed by reactive ion etching process as usual.
Sidewall 16 with 5in2 membrane on the side of flowering B
b to insulate the surfaces of the base extraction electrodes 15A and 15B. At this point, the width 1 to the opening 17 exposing the first base region 12A is approximately 0.4 μm.
Further, the width 1□ of the opening 17B exposing the second base region 12B is about 2.6 μm.

FIG. 2 (see di) Next, a layer of 0.2 to 0.3 μm was deposited on the above substrate by CVD method.
A non-topped poly-Si layer 18 having a thickness of about m is formed.

Here, the opening 17A with a small flowering width that exposes the base region 12A is completely filled with the poly-Si layer 18, and the upper poly-Si layer 18 becomes almost flat, and the opening 17A above the internuclear pore 17A is completely filled with the poly-Si layer 18. A non-doped poly-Si layer 18 having a thickness tl of approximately 0.9 to 1 μm, which is the sum of the depth of the poly-Si layer 18 and the thickness of the poly-Si layer 18, is deposited, and the opening exposing the base region 121+ is Opening hole 17B with extremely large hole width
A non-doped poly-Si layer 18 having a thickness t2 of approximately 0.2 to 0.3 μm, which is equal to the formation thickness, is deposited thereon.

From this figure onwards, the SiO□ film 16a and the SiO□ film sidewall 16b are collectively referred to as the SiO□ film 16.

Then, for example, the injection voltage is 5QKeV and the dose is 1×1.
016C Under conditions of approximately 2, ^S'', which is an emitter impurity, is selectively ion-implanted into the upper layer of the non-doped poly-Si layer 18. 19 indicates an As'' implanted region.

Referring to FIG. 2(e), the As introduced into the upper layer of the non-doped poly-Si layer 18, that is, the As+ implanted region 19, is removed by heat treatment at a high temperature of, for example, 1150° C. for about 20 seconds. Intrinsic base region 12A via layer 18
and rapidly diffuse into 12B. This diffusion causes 0.
In the intrinsic base region 12A directly under the opening 17A, which has a thick poly-Si layer 18 of about 9 to I μm on top, there is an impurity concentration of about 1020 cm″ff and a depth (dυ of 0.15 μrn).
The first n+ type emitter region 20^ of about 0.2 to 0
．． There is an impurity concentration of 1 in the intrinsic base region 12B directly under the opening 17B, which has a thin poly-Si layer 18 of about 3 μm on top.
Approximately 020c111-3, depth (d2) is 0.25 to 0
．． A second n-type emitter region 20B having a thickness of about 3 μm is formed.

Therefore, the remaining width B of the base of the first bipolar transistor Tr is approximately 0.15 to 0.25 μm, resulting in a low h
yt, the second bipolar transistor Tr2
The remaining width B2 of the base is approximately 0.1 μm, resulting in a high hF
I: is formed.

After referring to FIG. 2 (fl), a wiring material such as an aluminum (AI) layer is formed on the substrate by a conventional method, and the A1 layer and poly-Si layer are formed.
Layer 18 is simultaneously patterned to form an n" type poly-Si layer 1
A in contact with emitter region 2OA, 2011 through 8
I emitter wirings 21A, 21B, base wirings (not shown) through the base lead-out electrodes 15A, 15B, collector wirings (not shown) through the n-type substrate 11, etc. are formed to form a plurality of bipolar wires with different hFE values. A semiconductor device having transistors on one semiconductor substrate is completed.

Note that the non-doped silicon layer used as the diffusion source of the emitter impurity may be single silicon or amorphous silicon.

Further, impurities may be introduced into the upper part of the silicon layer by a deposition method.

Furthermore, the present invention is of course applicable not only to the npn type semiconductor device mentioned above but also to pnp type bipolar semiconductor devices.

〔Effect of the invention〕

As described above, the present invention provides a method for manufacturing a bipolar transistor in which an emitter region is formed by solid-phase diffusion of impurities through a silicon layer grown on a substrate J-. 12. The depth of the emitter region is controlled by taking into consideration the thickness of the silicon layer and the opening width of the emitter window. Can be formed.

Therefore, according to the present invention, the manufacturing process of a semiconductor device having a plurality of bipolar transistors having different hFEs is greatly simplified, which is effective in reducing the cost of the semiconductor device and shortening the manufacturing time.

[Brief explanation of the drawing]

FIG. 1 (aj to (C)) are process cross-sectional views showing the principle of the present invention, and FIGS. 2 (a) to (f) are process cross-sectional views of an embodiment of the present invention. In the figures, 1 is Semiconductor substrate, 2A and 211 are Hess area, 3 is an insulating film, 48 and 41! are emitter windows, 5.5 and 5B are Hannontorb silicon layers, 6 are S conductive layers, 7A and 7B are n' type emitter region, Lo, tg does not indicate the thickness of the silicon layer.

Claims (1)

[Claims] An emitter window is formed in an insulating film on a base region of one conductivity type, a non-doped silicon layer is formed on the insulating film including the inside of the emitter window, and an upper layer of the non-doped silicon layer is formed. An opposite conductivity type impurity is selectively introduced into the base region, and the opposite conductivity type impurity is diffused into the base region through the emitter window and the non-doped region of the silicon layer by heat treatment, thereby forming opposite conductivity into the base region. forming a plurality of bipolar transistors on one semiconductor substrate using a step of forming a type emitter region, and changing the aperture width of the plurality of emitter windows, and adjusting the aperture width of the emitter window and the silicon layer. The depth of the emitter region is controlled depending on the thickness, so that a first emitter region shallower than a second emitter region formed under an emitter window with a small opening width is formed under an emitter window with a large opening width. 1. A method of manufacturing a semiconductor device, comprising: forming an emitter region.