JPH0831474B2 - Method for manufacturing semiconductor device - Google Patents

Description

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a plurality of bipolar transistors having different current amplification factors, and to provide a manufacturing method in which steps are simplified. For the purpose, an emitter window is opened in the insulating film on the one conductivity type base region, a non-doped silicon layer is formed on the insulating film including the inside of the emitter window, and the non-doped silicon layer is selectively formed on the upper layer part. An opposite conductivity type impurity is introduced into the base region through the emitter window and the non-doped region of the silicon layer by heat treatment to introduce an opposite conductivity type impurity into the base region. Forming a plurality of bipolar transistors on one semiconductor substrate by using the step of forming a plurality of emitter windows, and changing the aperture widths of the plurality of emitter windows. The depth of the emitter region is controlled by the balance between the opening width and the thickness of the silicon layer, and the second opening is formed under the emitter window with the small opening width and under the emitter window with the large opening width. The first emitter region shallower than the first emitter region is formed.

[Industrial applications]

The present invention relates to a method for manufacturing a semiconductor device, and more particularly to a method for manufacturing a semiconductor device including a plurality of bipolar transistors having different current amplification factors.

With the diversification of needs, functions, and higher performance, various demands are being made on the current amplification factor (h _FE ) of bipolar transistors, and bipolar transistors with different h _FE sizes are installed on one substrate. Semiconductor circuit
IC is required.

However, in the field of semiconductors in which cost competition is fierce, it is not possible to increase the number of manufacturing processes to meet the above demands, and it is desired to develop a manufacturing method without increasing the number of manufacturing processes.

[Conventional technology]

In the bipolar transistor, transistors having different sizes of h _FE change the depth of the emitter to change the remaining width of the base.

The emitter injection efficiency is changed by changing the emitter concentration.

Change the depth of the base to change the remaining width of the base.

By changing the concentration of the base, the injection efficiency of the emitter is changed.

And the like.

In the conventional manufacturing method, in order to achieve the above means, for example, the impurity diffusion temperature is changed to change the depth of the emitter or base, and the impurity ion implantation is performed twice to change the concentration of the emitter or base. It was dealt with by increasing the number of steps such as carrying out.

[Problems to be Solved by the Invention]

However, in the conventional manufacturing method involving an increase in the number of steps, an increase in the number of steps and manufacturing cost is unavoidable, which causes problems in terms of shortening delivery time and reducing costs.

Therefore, an object of the present invention is to provide a manufacturing method in which the steps are simplified.

[Means for solving the problem]

The above-mentioned problem is to form an emitter window in an insulating film on one conductivity type base region, form a non-doped silicon layer on the insulating film including the inside of the emitter window, and select an upper layer portion of the non-doped silicon layer. The opposite conductivity type impurity is diffused into the base region through the emitter window and the non-doped region of the silicon layer by heat treatment, and the opposite conductivity type emitter is introduced into the base region. A step of forming a plurality of bipolar transistors on one semiconductor substrate by using a step of forming a region, and changing the opening widths of the plurality of emitter windows, the opening widths of the emitter windows and the thickness of the silicon layer; The depth of the emitter region is controlled by a trade-off between the two, and the depth is smaller in the lower portion of the emitter window having the small opening width than in the second emitter region formed at the lower portion of the emitter window having the large opening width. It is solved by a method of manufacturing a semiconductor device according to the present invention for forming a first emitter region.

[Work]

1A to 1C are process sectional views showing the principle of the present invention.

In the method of the present invention, a plurality of, for example, p-type base regions (2A) and (2B) having the same depth are provided as shown in FIG.
A plurality of emitter windows (4A), (4B) having different aperture widths are formed in an insulating film (3) on a semiconductor substrate (1) in which the insulating film (3) is formed, and the insulating film (3) includes the inside of the emitter window. A non-doped silicon layer (5) having a predetermined thickness is formed thereon. By doing this, the aperture width (W _A ) of the emitter windows (4A) and (4B),
(W _B ) and the thickness of the silicon layer (5), the thickness t _A of the silicon layer (5A) on the emitter window (4A) with a small opening width is on the emitter window (4B) with a large opening width. Thicker than the thickness t _B of the silicon layer (5B).

In the figure, the opening width (W _A ) of the small emitter window (4A) is less than twice the growth thickness (t) of the silicon layer, and the opening width (W _B ) of the large emitter window (4B) is silicon. This is a typical example where the growth is controlled to be significantly larger than twice the growth thickness (t) of the layer.

After forming the non-doped silicon layer (5) in this way, according to the method of the present invention, impurities for selectively forming an emitter are selectively formed on the upper layer portion of the non-doped silicon layer (5) as shown in FIG. For example, arsenic (As ⁺ ) is introduced by ion implantation (II). (6) shows an As introduction layer.

Then, heat treatment is performed at high temperature for a short time, and the emitter window (4A)
And (4B) upper As introduction layer (6) to the emitter window (4
A), (4B) and through the silicon layers (5A), (5B) on the emitter windows (4A), (4B).
A) and (2B) are diffused with impurities, and as shown in (c) of the same figure, the emitter windows (4A) and (4B) have a n ⁺ -type first emitter region (7A), 2 emitter regions (7
B) is formed. At this time, as described above, the silicon layer (5A)
Has a large thickness t _A , and has a long diffusion distance of impurities to the base region (2A).
A shallow first emitter region (7A) is formed in the lower part of (A), and the thickness t _B of the silicon layer (5B) is formed thin so that the diffusion distance to the base region (2B) is short and the aperture width is large. A deep second emitter region (7B) is formed under the window (4B).

As described above, according to the method of the present invention, a plurality of emitter regions having different depths can be formed by one solid-phase diffusion step, so that the manufacturing process of a semiconductor device having a plurality of bipolar transistors having different h _FE can be significantly performed. It is simplified to.

〔Example〕

An embodiment of the present invention for manufacturing a semiconductor device having a plurality of bipolar transistors having an isoplanar type having a poly-Si extraction base electrode and having different h _FE values will be described with reference to FIG. Specific steps will be described with reference to process cross-sectional views shown in FIGS.

See FIG. 2 (a). First, a small bipolar transistor (Tr ₁ ) having a low h _FE is formed on the surface portion of the n-type semiconductor substrate 11 serving as a collector by a selective oxidation method according to a normal bipolar transistor forming method. For example, region 1 with a width of about 3 μm
2A and a field oxide film 13 for separating and defining a region 12B having a width of about 5 μm in which a large bipolar transistor (Tr ₂ ) having a high h _FE is formed.

See FIG. 2 (b). Then, a poly-Si layer having a thickness of about 0.5 μm is formed on the substrate, and, for example, boron (B) is introduced at a high concentration into the poly-Si layer to impart conductivity. After that, a silicon dioxide (SiO ₂ ) film having a thickness of about 2000Å is formed on the poly-Si layer by thermal oxidation or a CVD method, and predetermined patterning is performed by an ordinary method to form the first and second transistors. The regions 12A and 12B are covered with the SiO 2 film and extend over the insulating film 13 and cover the edges.
_The frame-shaped first and second poly-Si base extraction electrodes 15A and 15B having the _two films 16a are formed. Here, the opening width W ₁ exposing the substrate surface of the first poly-Si base extraction electrode 15A is, for example, about 0.8 μm, and the opening width W exposing the substrate surface of the second poly-Si base extraction electrode 15B. ₂ is formed to about 3 μm.

Then, by heat treatment as usual at about 1000 ° C., B is solid-phase diffused from the base extraction electrodes into the transistor forming regions 12A and 12B to form p ⁺ -type external base regions 17A and 17B, and then the base extraction electrodes 15A and 15B. With boron as a mask, boron (B) is introduced to form the transistor forming regions 12A and 12B.
For example, an equal depth of about 0.3 to 0.4 μm, and 5 × 10 ¹⁸
p-type first base region having an impurity concentration of about cm ^-3
14A and the second base region 14B are formed.

Here 14A and 14B come to be referred to as the intrinsic base or interior base region.

See FIG. 2 (c). Then, a SiO film having a thickness of about 2000Å is formed on the substrate by the CVD method.
₂ films are formed and reactive ion etching is performed as usual to form Si on the sides of the openings of the base extraction electrodes 15A and 15B.
A side wall 16b made of an O ₂ film is formed to insulate the surfaces of the base lead electrodes 15A and 15B. At this point, the first
The width W ₁₁ of the opening 17A that exposes the base region 12A is about 0.4 μm.
And the width W of the opening 17B exposing the second base region 12B.
₁₂ is about 2.6 μm.

Next, referring to FIG. 2D, a non-doped poly-Si layer 18 having a thickness of about 0.2 to 0.3 μm is formed on the substrate by the CVD method. Here, the opening 17A having a small opening width that exposes the base region 12A is formed by the poly-Si layer 18
And the upper poly-Si layer 18 becomes almost flat, and the thickness of the poly-Si layer 18 is about 0.9 to 1 μm. A non-doped poly-Si layer 18 having a thickness t ₁ is deposited, and a thickness of about 0.2 to 0.3 μm, which is equal to the formation thickness, is formed on the opening 17B having a remarkably large opening width that exposes the base region 12B. An undoped poly-Si layer 18 having a depth t ₂ is deposited.

Note that, from this figure onward, the SiO ₂ film 16a and the SiO ₂ film sidewall 16b are collectively referred to as the SiO ₂ film 16.

Then, for example, injection voltage 50 KeV, dose 1 × 10 ¹⁶ cm
As ⁺ , which is an emitter impurity, is selectively ion-implanted into the upper layer portion of the non-doped poly-Si layer 18 under a condition of about ^-2 . 19 is
Shows As ⁺ implant region.

As shown in FIG. 2 (e), the As introduced into the upper layer portion of the non-doped poly Si layer 18, that is, the As ⁺ implantation region 19 is subjected to a high-temperature short-time heat treatment at, for example, 1150 ° C. for about 20 seconds, and the non-doped poly under the As is implanted.
It diffuses rapidly through the Si layer 18 and into the intrinsic base regions 12A and 12B. Due to this diffusion, thick poly-Si of about 0.9-1 μm
The first n ⁺ -type emitter region 20A having an impurity concentration of about 10 ²⁰ cm ⁻³ and a depth (d ₁ ) of about 0.15 μm is formed in the intrinsic base region 12A immediately below the opening 17A having the layer 18 at the top. A second layer having an impurity concentration of about 10 ²⁰ cm ⁻³ and a depth (d ₂ ) of about 0.25 to 0.3 μm in the intrinsic base region 12B immediately below the opening 17B having a thin poly-Si layer 18 of about 0.3 μm. N ⁺ type emitter region 2
0B is formed.

Therefore, the remaining width B _{1 of the} base of the first bipolar transistor Tr ₁ is about 0.15 to 0.25 μm, and the low h _FE is formed, and the remaining width B _{2 of the} base of the _second bipolar transistor Tr ₂ is about 0.1 μm. And formed with high h _FE .

See FIG. 2 (f). Thereafter, a wiring material, for example, an aluminum (Al) layer is formed on the substrate by a usual method, and the Al layer and the poly-Si layer 18 are formed.
Is patterned at the same time, and Al emitter wirings 21A and 21B, which are in contact with the emitter regions 20A and 20B through the n ⁺ type poly-Si layer 18,
Also, a base wiring (not shown) via the base extraction electrodes 15A and 15B, a collector wiring (not shown) via the n-type substrate 11 and the like are formed to form a plurality of bipolar transistors having different values of h _FE on one semiconductor substrate. To complete the semiconductor device.

The non-doped silicon layer used as the diffusion source of the emitter impurities may be single silicon or amorphous silicon.

Impurities may be introduced into the upper layer of the silicon layer by a deposition method.

In addition, the present invention is not limited to the above npn type and is of course applied to a pnp type bipolar semiconductor device.

〔The invention's effect〕

As described above, according to the present invention, in the method for manufacturing a bipolar transistor in which the emitter region is formed by solid phase diffusion of impurities through the silicon layer grown on the substrate, the thickness of the silicon layer and the opening of the emitter window are set. By controlling the depth of the emitter region in consideration of the hole width, it is possible to form a plurality of emitter regions having different depths by one solid phase diffusion step.

Therefore, according to the present invention, the manufacturing process of a semiconductor device having a plurality of bipolar transistors having different h _FE is greatly simplified, which is effective in reducing the cost of the semiconductor device and shortening the manufacturing turn.

BRIEF DESCRIPTION OF THE DRAWINGS FIGS. 1A to 1C are process sectional views showing the principle of the present invention, and FIGS. 2A to 2F are process sectional views of one embodiment of the present invention. Is. In the figure, 1 is a semiconductor substrate, 2A and 2B are base regions, 3 is an insulating film, 4A and 4B are emitter windows, 5 and 5A and 5B are non-doped silicon layers, 6 is an As introduction layer, and 7A and 7B are n ^+. The type emitter regions, t _A and t _B indicate the thickness of the silicon layer.

Claims (1)

[Claims] 1. An emitter window is opened in an insulating film on a base region of one conductivity type, a non-doped silicon layer is formed on the insulating film including the inside of the emitter window, and the non-doped silicon layer is formed on an upper layer portion of the non-doped silicon layer. An impurity of opposite conductivity type is selectively introduced, and the impurity of opposite conductivity type is diffused into the base region through the emitter window and through the non-doped region of the silicon layer by heat treatment so as to have opposite conductivity type in the base region. A step of forming a plurality of bipolar transistors on one semiconductor substrate by using a step of forming an emitter region, and changing the opening widths of the plurality of emitter windows, the opening widths of the emitter windows and the thickness of the silicon layer. The depth of the emitter region is controlled depending on the balance with the depth of the second emitter region formed below the emitter window having a small opening width and below the second emitter region having a large opening width. Method of manufacturing a semiconductor device and forming a first emitter region.