JPH0136259B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to gate turn-off (GTO) thyristor structures.

The conventional structure of a GTO thyristor was as shown in FIG. 1 or 2. The structure shown in FIG. 1 is called a split cathode type in which ₂ strip-shaped cathode N layers and ₂ gate P layers are arranged so as to be intersected with each other in plan view. There is no problem with this thyristor if it has a small current, but if it has a large current of several hundred amperes or more, the cathode _N2
There is a problem of electrical insulation between the external electrode 1 to which the layers are bonded and the gate electrode 2 to which the gate P ₂ layer is bonded, and the structure becomes complicated, resulting in an increase in manufacturing costs. The conventional thyristor shown in Fig. 2 has a low-resistance gate layer P ₂ ⁺⁺ embedded in the P ₂ base layer, and this thyristor does not require the cathode N ₂ layer to be divided. Although it is a simple structure with a donut circle shape, there is a problem that the internal resistance of the gate layer P ₂ ⁺⁺ , that is, the lead-out resistance to the gate electrode 3 is relatively large compared to the external gate electrode. To reduce this internal resistance, a buried layer P ₂ ⁺⁺
It is possible to reduce the distance between the
The disadvantage is that the loss when the thyristor conducts is large.

SUMMARY OF THE INVENTION An object of the present invention is to provide a GTO thyristor that has improved turn-off performance by reducing the internal resistance of the gate electrode and narrowing the width of the cathode conduction region, as well as enabling high frequency operation.

Figure 3 shows a conceptual diagram of the present invention, in which a cathode _N2 layer is formed in the shape of a wide strip, and a buried gate with a low resistance layer _P2 ⁺⁺ is formed in the _P2 layer corresponding to the central part of the _N2 layer. layer 4
are distributed, and the P ₂ layer sandwiched between the N ₂ layers has a surface gate layer 5 made of another high impurity layer from the surface.
(P ₂ ⁺⁺ ) is distributed and disposed on the surface of the surface gate layer 5, and an oxide film 6 is distributed over the N ₂ layer so that when the cathode electrode 7 is covered with the entire N ₂ layer, the N ₂ The structure prevents a short circuit between the layer and the gate layer 5,
The gate action of both the buried gate layer 4 and the surface gate layer 5 turns off the load current flowing through the _N2 layer. 8 is an anode electrode. The planar characteristics of the buried gate layer 4, surface gate layer 5, and _N2 layer will be explained below.

In high-frequency GTO thyristors, where short turn-on and turn-off times are important, it is desirable that the effective cathode _N2 layer width (Wo in Figure 2) be narrow; The effect of autodoping during epitaxial single crystal growth shortens Wo, which has a negative effect on turn-on operation. Therefore, in the present invention, as shown in FIG. 4, an enlarged view of the main part,
By providing the surface gate layer 5 in the portion sandwiched between _{the two} N layers, although the width Wb of the buried gate layer 4 is reduced, the effective width _WN of the cathode layer is narrowed, and the distance between the buried gate layers 4 is reduced. Increase Wg to eliminate the effects of autodoping. In addition, by making the width _WN of the effective cathode layer extremely small, the gate current required for turn-off can be reduced, that is, the turn-off gain can be increased, and both the buried gate layer 4 and the surface gate layer 5 can work together to reduce the gate current required for turn-off. By reducing the internal gate resistance of the gate, the turn-off speed is further increased. Furthermore, by insulating the surface gate layer 5 with an oxide film, the main electrode 7 on the cathode side does not need to be formed separately, which facilitates its formation and allows a large current to flow.

Specifically, the widths of the buried gate layer 4 and the surface gate layer 5 are as follows: W _N = 100μ (enables operation at 100KHz or higher), Wb = 250μ, Wd = 250μ, We =
300μ, the buried gate layer spacing Wg can be set to 750μ. This is the effective cathode width Wo in Figure 2.
= 100μ, which means that the buried gate layer spacing can be increased approximately five times as much as 100μ or less.

Next, a comparison between the conventional device shown in FIG. 2 and the device based on the present invention will be shown using the results of a prototype experiment. Specific resistance 50Ω
-cm N-type silicon substrate with gallium (Ga) on both sides.
A P 1 N 1 P 2 layer is formed by diffusing P ₁ N ₁ P ₂ layer at a surface concentration of 5×10 ⁷ to a depth of 30 μm, and then a high concentration boron layer that will become a buried gate layer is buried on the surface of the P ₂ layer using a selective diffusion method using an oxide film. to spread. To form this buried gate layer, Wo=100μ for the conventional device and Wg=100μ for the device of the present invention.
It was set to 750μ. In both cases, the boron diffusion results were a surface concentration of 2×10 ²⁰ and a diffusion depth of 10 μm. Following this diffusion, a P type single crystal layer with a resistivity of 5 Ω-cm was epitaxially grown on the entire surface of the P ₂ layer to a thickness of 25 μm.

Next, in the device of the present invention, the cathode N ₂ layer is a rectangular 4 mm long strip with a width (2W _N + W _b ) of 450 μm and a spacing (We) of 300 μm, and is windowed into the oxide film on the surface of the epitaxial layer. Formed by diffusing phosphorus. On the other hand, in the conventional element, the oxide film was exposed in concentric circles with a width of 4 mm, and then phosphorus was diffused to form an N ₂ layer and an N ₃ layer. The diffusion result at this time is the surface concentration 1×
10 ²⁰ , and the diffusion depth was 8μ. Next, in _the device of the present invention, the width is
Wd = 250μ, the length is N ₂ layer is divided, and boron is diffused at a high concentration to a surface concentration of 2×10 ²⁰ and a diffusion depth of 6μ using a selective diffusion method, and then an oxide film is formed on the entire surface using a low-temperature oxidation method. did. This oxide film formation was performed in the same manner as in the conventional element.

Next, the anode of both the conventional element and the present invention element is
Gold was applied to the _P1 layer side, and an anode electrode was formed by gold diffusion treatment at 850°C for 30 minutes. Next, in the device of the present invention, the oxide film on the _N2 layer side is removed, leaving the oxide film 6.
In the conventional device, the oxide film was removed leaving the surface of the P ₂ layer sandwiched between the N ₂ layer and the N ₃ layer, and aluminum was deposited to a thickness of 10 μm on the entire surface to form the cathode side and gate electrode. FIG. 5 is a plan view of the device of the present invention viewed from the cathode side, and FIG. 6 is a sectional view taken along line VV'. In the figure, 9 and 9' are gate electrodes.

The results of comparing the characteristics of the conventional device and the device of the present invention are as follows:
While the conventional device had a large voltage drop and was unable to operate as a thyristor to maintain the on state with a gate current, the device of the present invention can turn on normally with a gate current of 0.5A and has a voltage drop of 10A/cm ² at 1.8V
It was hot. Furthermore, the device of the present invention was able to achieve high-speed operation with switching speeds of 3 μs or less for both on and off switching.

As described above, according to the present invention, it is possible to substantially reduce the effective cathode width, increase the turn-off speed, reduce the gate current required for turn-off, and reduce the gate internal resistance.

[Brief explanation of drawings]

Fig. 1 is a structural diagram of a conventional cathode split type GTO thyristor, Fig. 2 is a structural diagram of a conventional buried gate type GTO thyristor, and Fig. 3 conceptually shows the present invention.
GTO thyristor structure diagram, FIG. 4 is an enlarged view of main parts for explaining the present invention, FIG. 5 is a plan view of the GTO thyristor based on the present invention, and FIG. 6 is along the line V-V' in FIG. FIG. 4... Buried gate layer, 5... Surface gate layer, 6... Oxide film, 7... Cathode electrode, 8... Anode electrode,
9, 9'...Gate electrode.

Claims (1)

[Claims] It has four layers of 1 P ₁ N ₁ P ₂ N ₂ , and the cathode N ₂ layer is formed separately, and the portion sandwiched between the cathode N ₂ layers is P _{2 .}
A surface gate layer 5 having a higher impurity concentration than the _P2 layer is formed in the layer, and a _P2 layer facing the cathode _N2 layer has a cathode _N2 layer facing the center of the cathode _N2 layer. A gate turn-off thyristor characterized by a structure in which a low-resistance buried gate layer 4 whose width is smaller than the width of the gate turn-off thyristor is formed. 2. In claim 1, an oxide film 6 is formed on the surface of the front gate layer 5 in a dispersed manner so as to extend over the ends of the cathode N2 layers on both sides of the gate layer ₅ , and _N2 layer and oxide film 6
A gate turn-off thyristor characterized by having a cathode electrode integrally formed on its surface.