JPH0147063B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION (1) Technical field to which the invention pertains The present invention relates to an improvement in a digital phase periodic circuit used in a phase modulation type receiving device or the like.

(2) Description of Prior Art Conventionally, this type of digital phase-locked circuit basically consists of a clock oscillator 1, a counter 2, decoders 3 and 4, a phase comparator 5, and a correction amount, as shown in FIG. It consists of a calculator 6 and a correction signal generator 7, and has the characteristics of short time until phase synchronization is established and little phase jitter in the output signal, but it has the following drawbacks.

In FIG. 1, when considering the delay time of the correction timing in critical path A, first, counter 2
The output signal of the first decoder 3, which decodes the output of , with a predetermined value, is input to the correction signal generator 7, which generates correction timings S ₁ to S ₈ . Correction timing S ₂ ~ _{S 8}
Since the timing is determined by the clock Sc in the shift register 701, the delay time is not large, but in the case of correction timing _S1 , the clock is determined by the counter 2.
Since the signal timed by Sc goes around the critical path A without being retimed midway, the delay is considerably larger than the correction timings S ₂ to _{S 8} .

Due to the above-mentioned drawbacks, it is not necessarily possible to cope with the situation of increasing clock speed.

(3) Purpose of the Invention The purpose of the present invention is to review the critical path in order to enable the use of high-speed clocks in existing digital phase synchronization circuits, improve the above-mentioned drawbacks, and create a digital phase synchronization circuit that can achieve faster operation. The purpose is to provide circuits.

(4) Structure of the Invention According to the present invention, a clock oscillator, a counter that counts clocks, first and second decoders that determine whether the counted value has reached a predetermined value, and the second decoder A phase comparator that compares the output of the input signal with the phase of the input signal, a correction amount calculator that calculates a correction amount according to the phase difference output from the phase comparator, and a correction value calculated by the correction amount calculator. one flip-flop circuit is provided between the first decoder and the correction signal generator and between the correction signal generator and the counter. However, in order to correct the 2-bit delay caused by the flip-flop, there is obtained a digital phase synchronization circuit characterized in that the decoded value of the first decoder is advanced by 2 bits.

(5) Embodiment FIG. 2, which is an embodiment of the present invention, will be described in detail below with reference to FIGS. 1 and 3. 1st
In the figure, considering the critical path A, the output signal counted and timed by the counter 2 by the clock Sc shown in FIG.
The decoder 3 decodes the data using the Nth clock (N is an integer) as shown in FIG.
is input to the selection selector 702. Here, the signal input to the shift register 701 is the clock
The delay is not large because the timing is taken again by the clock Sc, but since the signal _S1 input to the selector 702 is not retimed by the clock Sc on the way, the signal S1 input to the selector 702 is not retimed by the clock Sc. The delays t ₂ , t ₃ , and t ₇₀₂ of the selector 3 and the selector 702 are added. This delay time is clock Sc
There is no problem if it is within one cycle time of the clock.
As the speed of Sc increases, the delay time decreases by 1 of the clock Sc.
The cycle time may be exceeded. These drawbacks of the conventional digital phase-locked circuit described above can be avoided according to an embodiment of the present invention shown in FIG. In FIG. 2, similarly considering the critical path B, the signal counted by the counter 2 is first decoded by the first decoder 3 at the N-2th clock as shown in FIG. The waveform input to the retiming flip-flop 8 is delayed by one bit as shown in E, and has almost no delay relative to the clock Sc. Furthermore, even when the output signal of this flip-flop 8 is input to the selector 702, the output signal is retimed by the flip-flop 9 for retiming, and the relative delay with respect to the clock Sc is in this case. There are almost no As described above, according to the present invention, the delay t ₂ +t _{3 +702} in the critical path A in FIG. 1 is reduced to only the delay x ₉ of the retiming flip-flop, and the critical path can be significantly improved. In FIG. 2, the decoding timing of the first decoder 3 is set to N-2 with respect to the first decoder of FIG. This is to provide the same function as the circuit configuration shown in FIG.

(6) Effects of the Invention As explained above, the present invention has the effect of being able to sufficiently cope with higher speed clocks without impairing the structure and function of existing digital phase synchronized circuits.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the basic configuration of a digital phase synchronized circuit used in the present invention, and FIG. 2 is a block diagram showing an embodiment of the present invention. Further, FIG. 3 is a diagram showing the signal timing of each part in FIGS. 1 and 2. In the figure, 1... clock oscillator, 2...
... Counter, 3, 4 ... First and second decoders, respectively, 5 ... Phase comparator, 6 ... Correction amount calculator, 7
...Correction signal generator, 8, 9...Flip-flop for retiming, 701 is a shift register,
702...Selector, Si...Input signal, Sc...Clock, _S1 to _S8 ...Each correction timing, I...
Timing of clock Sc, B... Output timing of the first decoder 3 in FIG. 1, C... Output timing of the selector 702 in FIG. 1, D... Output timing of the first decoder 3 in FIG. 2, H... shows the output timing of the flip-flop 8 in FIG. 2, F... shows the output timing of the selector 702 in FIG. 2, and T... shows the output timing of the flip-flop 9.

Claims (1)

[Claims] 1. A clock oscillator, a counter that counts the clock, and a first device that determines whether the counted value has reached a predetermined value.
and a second decoder, a phase comparator that compares the output of the second decoder and the phase of the input signal, and a correction amount calculation that calculates a correction amount according to the phase difference output from the phase comparator. between the first decoder and the correction signal generator, and between the correction signal generator and the correction signal generator. A digital phase synchronization system characterized in that a flip-flop circuit is provided between the first decoder and the counter, and the decoded value of the first decoder is advanced by 2 bits in order to correct the 2-bit delay caused by the flip-flop. circuit.