JPH0156532B2 - - Google Patents

Description

[Detailed Description of the Invention] [Summary of the Invention] The present invention provides a -, - group compound semiconductor substrate with a zincblende structure, in which when the surface is a (111) plane, an insulating film on the surface exerts an effect on a channel region of the substrate. By utilizing the fact that the distribution of piezoelectric polarization charges due to stress is almost the same in all directions of 360 degrees, and the threshold voltage (Vth) is almost uniform regardless of the direction of the gate of the field effect transistor, it is possible to It is characterized by the (111) plane of the substrate.

[Industrial application field]

The present invention relates to improvements in semiconductor devices, particularly in semiconductor devices in which compound semiconductor field effect transistor elements are arranged in different directions, such as perpendicular to each other.

Microelectronics has become the foundation of modern industrial progress and has had a major impact on social life. Silicon (Si) semiconductor devices are currently the mainstay of microelectronics, and the miniaturization of transistor elements has had a great effect on speeding up and increasing the degree of integration.

Furthermore, in order to improve operating speed beyond the limits based on the physical properties of silicon, semiconductor devices using - and - group compound semiconductors such as gallium arsenide (GaAs), which have much higher carrier mobility than silicon, have been developed. has been done.

As a transistor using a compound semiconductor,
Although field effect transistors, especially shot-barrier field effect transistors, have been developed earlier due to their simple manufacturing process, efforts have been made to commercialize integrated circuit devices that take full advantage of their characteristics. It is being

[Conventional technology]

Schottky barrier field effect transistors (hereinafter abbreviated as MES FETs) are currently made of compound semiconductors.
In particular, there are many examples in which GaAs is used as the semiconductor material, and an example of its structure is shown in the schematic side sectional view of FIG.

In the conventional example shown in the figure, an n-type channel layer 12 is formed on the (100) plane of a semi-insulating GaAs substrate 11 by, for example, ion implantation, and a gate electrode is in short contact with this n-type channel layer 12. 13 are arranged.

Impurities are introduced by ion implantation using this gate electrode 13 as a mask, and n ⁺ type source and drain regions 14 with high impurity concentration are formed by the n type channel layer 12, and an insulating film 15 is deposited. , n ⁺ type source and drain regions 14 are provided with source and drain electrodes 16 in ohmic contact with them.

Integrated circuit devices are constructed using MES FETs as described above, and in order to increase their speed and integration,
As the miniaturization of MES FET elements progresses and their gate lengths are shortened, the range of variation in characteristics such as gate threshold voltage Vth from the expected value gradually increases, and Therefore, the direction of variation of this gate threshold voltage Vht differs.

FIG. 4 shows the crystal zone axis [011] direction in which the gate width direction is perpendicular to the GaAs (100) single crystal plane. MES
An example of gate threshold voltage Vth variation between FET and MES FET in the [011] direction is shown, and the gate length is 2 μm.
Below this level, there is a tendency for the [011] direction to fluctuate in the positive direction, while in the [011] direction it fluctuates significantly in the negative direction.

Therefore, in an integrated circuit device in which MES FET elements are arranged in two directions in this way, if the gate length deviates from the design value due to variations during the manufacturing process, for example, the gate threshold voltage Vth will vary significantly, making it difficult to achieve the intended purpose. Conventionally, the gate direction is usually limited to one direction because it is not possible to obtain the circuit operation as shown in FIG.

FIG. 5 shows an example in which the X and Y address decoder circuits of a storage device are constructed using MES FET elements whose gate widths are in the same direction.

As shown in FIG. 2A, the output line 24 of the X decoder 21 and the output line 25 of the Y decoder 22 are connected to the memory cell matrix 23 in a perpendicular direction. As for the X decoder 21, its output line 24 and
By aligning the width direction of the gate electrode G of the MES FET element with, for example, the [011] direction, it is possible to form an efficient pattern.

On the other hand, in the Y decoder 22, the MES FET
When the width direction of the gate electrode G of the element is aligned in the same [011] direction as the X decoder 21, this becomes a direction perpendicular to the output line 25. For this purpose, the gate electrode G is branched into a comb shape, and a large number of sources S and drains D are arranged to obtain a gate width equivalent to that of the X decoder 21, as shown in FIG. This pattern is shown in Figure b
The pattern is more complex than that of the previous one, and it is difficult to miniaturize and coarsely integrate it in both the design and manufacturing process.

As the causes of the so-called short channel effect mentioned above, attention has been focused on the penetration of highly concentrated impurities introduced into the source and drain regions 14 into the channel layer 12 and the effect of piezoelectric polarization that produces a semiconductor substrate mainly due to the insulating film 15. has been done.

Changes in characteristics due to this piezoelectric polarization are caused by MES FET
Insulating film 1 provided in contact with the semiconductor substrate of the element
5. Piezoelectric polarization is generated in the compound semiconductor substrate due to stress exerted on the semiconductor substrate by the gate electrode 13, etc.;
The gate threshold voltage Vth changes because the carrier distribution in the channel layer 12 changes and the shot depletion layer expands and contracts, and the polarity of the piezoelectric polarization determined by the stress direction and the crystal zone axis direction changes.
The direction of the fluctuation is the plus side or the minus side. (e.g. PMAsbeck et al.; IEEE
Transactions on Electron Devices, Vol.ED−
31, No. 10, Oct. 1984, pp. 1377-1380) [Problems to be solved by the invention] As explained above, in the conventional structure, fluctuations in the characteristics of the compound semiconductor field effect transistor cause shortening of the gate length. This makes it extremely difficult to arrange orthogonally.

Beyond this current situation, miniaturized MES
There is a strong demand for a semiconductor device whose characteristics are stable even when FET elements are arranged in different directions, such as perpendicularly to each other, and whose degree of integration can be increased.

[Means for solving problems]

The above-mentioned problem is caused by - group of zincblende structure, -
The problem is solved by a semiconductor device according to the present invention, in which a plurality of field effect transistor elements are formed on the (111) plane of a group compound semiconductor substrate, and the field effect transistor elements include elements whose gate directions are different from each other. .

[Effect]

The present inventors have studied, for example, the stress generated in the GaAs compound semiconductor substrate, the material and thickness of the insulating film, the crystal plane of the semiconductor substrate, the crystal zone axis and the piezoelectric polarization state due to this stress, the gate threshold voltage and K value of the field effect transistor. We study the correlation between piezoelectric polarization and piezoelectric polarization states,
For example, when the insulating film is silicon dioxide (SiO ₂ ), the crystal plane of the GaAs single crystal substrate, the gate width direction and gate threshold voltage of an n-channel MES FET
The following results were obtained regarding the relationship with the direction of Vth variation.

Element formation diagram Gate width direction Vth variation direction (100) [011] Minus [011] Plus (111) B [112] Minus [110] Minus In other words, perpendicular [011] direction on the (100) plane and [011] ] direction, as mentioned above, the direction of Vth fluctuation is the opposite direction, whereas for example (111)
The direction of Vth variation is the same in the [112] direction and the [110] direction, which are orthogonal to each other on the B plane.

More specifically, when gate electrodes with gate width directions in the [112] and [110] directions are formed on the (111)A plane of a GaAs semiconductor substrate using, for example, tungsten silicide (WSi), and a SiO ₂ film is deposited. The distribution of the piezoelectric polarization charge is shown in FIGS. 2a and 2b. In the same figure, A is 1×10 ¹⁶ cm ^-3 or more, B is 5×10 ¹⁵ cm
^-3 or more, C is 1 x 10 ¹⁵ cm ^-3 or more, D is 5 x 10 ¹⁴ cm
A concentration of ^-3 or higher, 1 represents a negative charge, and no sign represents a positive charge.

As seen in Figures 2a and b, the piezoelectric polarization charge distributions in the orthogonal [112] and [110] directions on the (111)A plane match extremely well.
The same holds true for the other two sets of directions of the zone axes that are equivalent to [112] and [110], respectively. Also (111)
Regarding the B-plane, the sign of the piezoelectric polarization charge is reversed, but the distribution pattern shape is exactly the same as that of the (111) A-plane.

In this way, on the (111) plane, the piezoelectric polarization characteristics match well in any two mutually orthogonal directions,
The polarity of the piezoelectric polarization is the same even in two directions that are not perpendicular to each other.

Figure 6 shows [11
0], [112] The relationship between the gate threshold voltage and K value and the channel length when the gate width direction is set in the axial direction is shown. As can be seen from the figure, even if the channel length becomes shorter, the [110] and [112] axes fluctuate almost equally.

From the above data, it can be understood that the [110] and [112] axes have equivalent characteristics, but according to Figure 7, if the (111) plane is used, even if the gate axis direction is changed by 360 degrees. It can be seen that the gate threshold voltage and K value are almost the same.

In other words, even if the angle θ of the horizontal axis is changed, (111)
In the case of the A-plane or (111)B-plane, the gate threshold voltage hardly changes. On the other hand, in the case of the (100) plane, when the gate width direction changes, the gate threshold voltage also changes significantly. Therefore, it is understood that when the (111) plane is used, the gate threshold value is approximately the same regardless of the gate width direction of the field effect transistor, and the short channel effect is also approximately the same. However, it is generally convenient in the manufacturing process to arrange the gate electrodes in parallel and perpendicular directions to the cleavage plane of the substrate and cut them into square chips. Although the data shown in FIG. 7 is obtained by changing the angle by 0 to 90 degrees, it is clear that the same characteristics can be obtained even if the angle is changed by 90 to 360 degrees due to the symmetry of the crystal.

The reason why such characteristics are obtained is still unclear, but looking back at the invention, in the case of a compound semiconductor with a zincblende structure such as GaAs, the piezoelectric polarization charge on the (111) plane due to the crystal structure of the surface This is thought to be due to the fact that the distribution is uniform regardless of the axial direction. Therefore, not only GaAs but also other materials can have the same crystal structure if they have the same zinc blende structure, and the same effect can be obtained.

Therefore, the − group of the sphalerite structure (GaAs,
InSb, InAs, GaSb, InP, GaP, AlAs) and - group (CdTe, ZnTe, ZnSe, ZnS, CdS,
CdSe) etc. are also within the scope of the present invention.

Due to the characteristics of this (111) plane, no difference in piezoelectric polarization effect will appear between FETs formed on this plane with different gate directions, and even if the channel length is shortened, there will be no difference in the piezoelectric polarization effect between FETs with different gate directions. No difference in characteristics such as threshold voltage occurs.

〔Example〕

The present invention will be specifically explained below using examples.

FIG. 1 is a schematic plan view showing the process order of an embodiment of the present invention relating to an integrated circuit device having an E/D configuration using GaAs MES FET as a basic element.

In this example, E (enhancement) mode (hereinafter referred to as subscript E) and D (depletion) mode were
mode (hereinafter represented by subscript D) n-channel
An inverter made of MES FET elements is formed with respective gate width directions in the [110] direction (hereinafter represented by subscript 1) and the [112] direction (hereinafter represented by subscript 2).

Refer to FIG. 1a. For example, silicon (Si) is ion-implanted into the (111)B plane of a semi-insulating GaAs substrate 1 as described below to form an n-type channel region 2 of each element.

D mode channel regions 2 _D1 and 2 _D2 , energy 59kev, dose 1.7×10 ¹² cm ^-2 E mode channel regions 2 _E1 and 2 _E2 , energy 59kev, dose 0.9×10 ¹² cm ^-2 After ion implantation, A protective film (not shown) such as aluminum nitride (AIN) is provided on one surface of the substrate,
For example, activation heat treatment is performed at a temperature of 850° C. for about 15 minutes.

Refer to FIG. 1b. On the surface of the substrate 1, for example, W ₅ Si ₃ is deposited to a thickness of about 400 mm by sputtering or the like, and this is patterned to form each gate electrode 3. In this embodiment, the gate length is approximately 1 μm.

Refer to Fig. 1c. Using the gate electrode 3 as a mask, apply it to the substrate 1, for example.
Si at energy 175kev, dose 1.7×10 ¹³ cm
By implanting ions to about ^-2 and performing activation heat treatment at, for example, 750°C for about 10 minutes, an n ⁺ type source is formed.
A drain region 4 is formed.

See Figure 1 d For example, plasma chemical vapor deposition method (P-CVD method)
Then, a silicon nitride (SiNx) film (not shown) is formed to a thickness of about 500 nm, for example, and the gate electrode 3 is
It is deposited on the entire surface of the substrate 1 including the substrate.

Openings are formed in the SiNx film 5 on the n ⁺ type source and drain regions 4, and the source and
The drain electrode 5 and the like are formed to a thickness of about 250 nm.

In this example, two types of gates with orthogonal gate directions are used.
In the MES FET element, the difference in gate threshold voltage Vth for each of the D and E modes is only a few tens of millivolts at a gate length of 1 μm, and it is possible to use them completely equally.

Regarding the conventional decoder described above, both X and Y decoders can be obtained using MES FET elements having the same pattern, and it is possible to form an arbitrary integrated circuit.

Furthermore, although the above description is directed to GaAs MES FETs, other compound semiconductor materials may also be used, such as indium phosphorus (InP), indium gallium arsenide phosphide (InGaAsP), etc.
using group compound semiconductor substrate or bonded type,
Similar effects can be obtained by the method of the present invention for MIS type or high mobility field effect transistors (HEMT) that use a two-dimensional carrier gas near a heterojunction as a channel.

〔Effect of the invention〕

As explained above, according to the present invention, even if the gate directions of compound semiconductor field effect transistors are arranged in arbitrary mutually different directions and the channel length is shortened, characteristics such as gate threshold voltage can be made uniform. This makes it possible to reduce the difference in characteristics even in the case of orthogonal or oblique intersections, resulting in a great effect on the practical application of compound semiconductor integrated circuit devices.

[Brief explanation of drawings]

Figures 1a to d are schematic plan views showing the process order of an embodiment of the present invention, and Figures 2a and b are on the GaAs (111) A plane, with the gate width in the direction of the [112] or [110] axis. Distribution diagram of piezoelectric polarization charge when SiO ₂ film is deposited, Figure 3 is a schematic side sectional view showing a conventional example of MES FET, Figure 4 is a diagram showing a conventional example of MES FET characteristics, Figure 5 a is a schematic plan view showing an example of a decoder, FIGS. 5 b and c are schematic plan views showing a conventional example of the MES FET element of the decoder, and FIG. 6 is a (111) plane.
The gate width in GaAs substrate is [112], [11]
0] A graph showing the short channel effect in the case of the axial direction. FIG. 7 is a graph showing the change in gate threshold voltage when the gate direction is changed in the (111) plane or (100) plane of the GaAs substrate. In the figure, 1 is a semi-insulating GaAs substrate, 2 is an n
3 is a gate electrode, 4 is an n ⁺ type source and drain region, 5 is a source and drain electrode, subscript D is depletion mode, subscript E is enhancement mode, subscript 1 is gate width direction [110], The subscript 2 indicates the gate width direction [112].

Claims (1)

[Claims] 1. A compound semiconductor with a zincblende structure (111)
It has a substrate having a flat surface as a surface, and a plurality of field effect transistor elements formed on the surface of the substrate, and the field effect transistor elements include elements whose gate electrode directions are different from each other. semiconductor device.