JPH0338633U - - Google Patents
Info
- Publication number
- JPH0338633U JPH0338633U JP1989098578U JP9857889U JPH0338633U JP H0338633 U JPH0338633 U JP H0338633U JP 1989098578 U JP1989098578 U JP 1989098578U JP 9857889 U JP9857889 U JP 9857889U JP H0338633 U JPH0338633 U JP H0338633U
- Authority
- JP
- Japan
- Prior art keywords
- bare chip
- semiconductor bare
- semiconductor
- glass dam
- outer periphery
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Classifications
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
- H10W90/00—Package configurations
- H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
- H10W90/721—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors
- H10W90/724—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bump connectors between a chip and a stacked insulating package substrate, interposer or RDL
Landscapes
- Wire Bonding (AREA)
Description
第１図は本考案の実施例を示す平面構造図、第
２図は第１図のＡＡ′断面図である。
図に於いて１…基板、２…導体パターン、３…
半導体ベアチツプ、４…ランド部分、５…半田バ
ンプ、６…ガラスダムである。
FIG. 1 is a plan structural view showing an embodiment of the present invention, and FIG. 2 is a sectional view taken along line AA' in FIG. In the figure, 1...board, 2...conductor pattern, 3...
Semiconductor bare chip, 4...land portion, 5...solder bump, 6...glass dam.
Claims (1)
プを搭載し、かつ前記半導体ベアチツプの外周の
一部又は全部にガラスダムを設け、前記導体パタ
ーンと前記半導体ベアチツプを半田バンプを溶融
して接続して成る半導体装置に於いて、前記ガラ
スダムの内側エツジを前記半導体ベアチツプ外形
寸法より０．０５〜０．３mm大きくし、かつ前記
ガラスダムが前記半導体ベアチツプの外周の導体
パターン部分を断続的に取り囲んだ事を特徴とす
る半導体装置。 A semiconductor device comprising a semiconductor bare chip mounted on a substrate having a conductive pattern, a glass dam provided on a part or all of the outer periphery of the semiconductor bare chip, and the conductive pattern and the semiconductor bare chip connected by melting solder bumps. A semiconductor characterized in that the inner edge of the glass dam is 0.05 to 0.3 mm larger than the outer dimension of the semiconductor bare chip, and the glass dam intermittently surrounds a conductor pattern portion on the outer periphery of the semiconductor bare chip. Device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989098578U JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1989098578U JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0338633U true JPH0338633U (en) | 1991-04-15 |
Family
ID=31647665
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1989098578U Pending JPH0338633U (en) | 1989-08-24 | 1989-08-24 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0338633U (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347238A (en) * | 2018-04-03 | 2019-10-18 | 富士通电子零件有限公司 | Input equipment |
-
1989
- 1989-08-24 JP JP1989098578U patent/JPH0338633U/ja active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN110347238A (en) * | 2018-04-03 | 2019-10-18 | 富士通电子零件有限公司 | Input equipment |