JPH0187555U - - Google Patents

Info

Publication number
JPH0187555U
JPH0187555U JP1987184090U JP18409087U JPH0187555U JP H0187555 U JPH0187555 U JP H0187555U JP 1987184090 U JP1987184090 U JP 1987184090U JP 18409087 U JP18409087 U JP 18409087U JP H0187555 U JPH0187555 U JP H0187555U
Authority
JP
Japan
Prior art keywords
resin
semiconductor element
element mounting
mounting part
recess
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1987184090U
Other languages
English (en)
Other versions
JPH0526762Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1987184090U priority Critical patent/JPH0526762Y2/ja
Publication of JPH0187555U publication Critical patent/JPH0187555U/ja
Application granted granted Critical
Publication of JPH0526762Y2 publication Critical patent/JPH0526762Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/90—Bond pads, in general
    • H10W72/931—Shapes of bond pads
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/736—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked lead frame, conducting package substrate or heat sink
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/756—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked lead frame, conducting package substrate or heat sink

Landscapes

  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】
第１図はこの考案の一実施例の樹脂封止形半導
体装置に用いられるリードフレームの一部を示す
平面図、第２図は第１図の主要部分の平面図、第
３図は第２図の―線に沿つた断面図、第４図
は第１図ないし第３図に示すリードフレームを用
いた樹脂封止形半導体装置の断面図である。第５
図はこの考案の他の一実施例の樹脂封止形半導体
装置に用いられるリードフレームの主要部分の平
面図、第６図は第５図の―線に沿つた断面図
、第７図は第５図、第６図に示すリードフレーム
を用いた樹脂封止形半導体装置の断面図である。
第８図はこの考案の更に他の一実施例の樹脂封止
形半導体装置に用いられるリードフレームに設け
られた凹部の断面図、第９図はこの考案の更に他
の一実施例の同じく凹部の断面図である。第１０
図は従来の樹脂封止形半導体装置に用いられるリ
ードフレームの一部を示す平面図、第１１図は第
１０図のリードフレームを用いた樹脂封止形半導
体装置の断面図である。 図において、３は半導体素子載置部、４はリー
ド、６は半導体素子を載置する面、１０は樹脂、
１１は凹部、１２は樹脂連通口、１５は貫通穴で
ある。なお、各図中同一符号は同一または相当部
分を示す。

Claims (1)

  1. 【実用新案登録請求の範囲】 (1) 半導体素子を載置する面に設けた凹部とこ
    の凹部に連通する樹脂連通口とを有する半導体素
    子載置部、およびこの半導体素子載置部の周辺に
    配置させた複数のリードを備えたリードフレーム
    を樹脂で一体的にモールドしてなる樹脂封止形半
    導体装置。 (2) 凹部が半導体素子載置部の一端から他端ま
    での溝状で、樹脂連通口がこの溝の開口した両端
    部である実用新案登録請求の範囲第１項記載の樹
    脂封止形半導体装置。 (3) 溝の底部に貫通穴を有する実用新案登録請
    求の範囲第２項記載の樹脂封止形半導体装置。
JP1987184090U 1987-12-01 1987-12-01 Expired - Lifetime JPH0526762Y2 (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1987184090U JPH0526762Y2 (ja) 1987-12-01 1987-12-01

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1987184090U JPH0526762Y2 (ja) 1987-12-01 1987-12-01

Publications (2)

Publication Number Publication Date
JPH0187555U true JPH0187555U (ja) 1989-06-09
JPH0526762Y2 JPH0526762Y2 (ja) 1993-07-07

Family

ID=31475475

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1987184090U Expired - Lifetime JPH0526762Y2 (ja) 1987-12-01 1987-12-01

Country Status (1)

Country Link
JP (1) JPH0526762Y2 (ja)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2011514180A (ja) 2008-02-01 2011-05-06 アメリゴン インコーポレイティド 熱電デバイスのための凝縮体センサ及び湿度センサ

Also Published As

Publication number Publication date
JPH0526762Y2 (ja) 1993-07-07

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