JPH0189752U - - Google Patents

Info

Publication number
JPH0189752U
JPH0189752U JP1988159576U JP15957688U JPH0189752U JP H0189752 U JPH0189752 U JP H0189752U JP 1988159576 U JP1988159576 U JP 1988159576U JP 15957688 U JP15957688 U JP 15957688U JP H0189752 U JPH0189752 U JP H0189752U
Authority
JP
Japan
Prior art keywords
conductor
circuit board
brazed
conductor pin
semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP1988159576U
Other languages
Japanese (ja)
Other versions
JPH0536275Y2 (en
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1988159576U priority Critical patent/JPH0536275Y2/ja
Publication of JPH0189752U publication Critical patent/JPH0189752U/ja
Application granted granted Critical
Publication of JPH0536275Y2 publication Critical patent/JPH0536275Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages

Landscapes

  • Lead Frames For Integrated Circuits (AREA)

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第１図は従来のパツケージを回路基板に装着し
た構造断面図例、第２図はそのパツケージの平面
図、第３図は本考案にかかる半導体パツケージの
断面図、第４図は本考案の一実施例による半導体
実装回路装置の断面図、第５図は第４図における
要部拡大図、第６図は本考案の他の実施例による
半導体実装回路装置の断面図を示す。 図中、１はパツケージ、２は回路基板、３，６
は半田、４は導体ピン、５は銀鑞、１２は導体パ
ツド、２１は接続用の電極を示している。 Figure 1 is an example of a structural cross-sectional view of a conventional package mounted on a circuit board, Figure 2 is a plan view of the package, Figure 3 is a cross-sectional view of a semiconductor package according to the present invention, and Figure 4 is an example of a semiconductor package according to the present invention. FIG. 5 is an enlarged view of the main part of FIG. 4, and FIG. 6 is a cross-sectional view of a semiconductor packaged circuit device according to another embodiment of the present invention. In the figure, 1 is a package, 2 is a circuit board, 3, 6
1 is solder, 4 is a conductor pin, 5 is silver solder, 12 is a conductor pad, and 21 is a connection electrode.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 積層セラミツク基板の中央内部にＩＣチツプの
取付けられる半導体パツケージにおいて、回路基
板に対向する面上にメタライズ層として形成され
る複数個の導体パツドには、夫々バネ性を有する
導体ピンの一端が高融点金属で鑞づけされ、該導
体ピンの他端が前記回路基板上の被接続導体に当
接して鑞づけされていることを特徴とする半導体
実装回路装置。 In a semiconductor package in which an IC chip is mounted inside the center of a laminated ceramic substrate, a plurality of conductor pads formed as a metallized layer on the surface facing the circuit board each have one end of a conductor pin having a spring property with a high melting point. 1. A semiconductor mounted circuit device characterized in that the conductor pin is brazed with metal, and the other end of the conductor pin is brazed in contact with a conductor to be connected on the circuit board.
JP1988159576U 1988-12-08 1988-12-08 Expired - Lifetime JPH0536275Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1988159576U JPH0536275Y2 (en) 1988-12-08 1988-12-08

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1988159576U JPH0536275Y2 (en) 1988-12-08 1988-12-08

Publications (2)

Publication Number Publication Date
JPH0189752U true JPH0189752U (en) 1989-06-13
JPH0536275Y2 JPH0536275Y2 (en) 1993-09-14

Family

ID=31440912

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1988159576U Expired - Lifetime JPH0536275Y2 (en) 1988-12-08 1988-12-08

Country Status (1)

Country Link
JP (1) JPH0536275Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016048728A (en) * 2014-08-27 2016-04-07 株式会社村田製作所 Conductive post and manufacturing method of multilayer substrate using conductive post

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559746A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Semiconductor device and its mounting circuit device
JPS5743452A (en) * 1980-08-28 1982-03-11 Mitsubishi Electric Corp Mounting structure for integrated circuit substrate
JPS5791586A (en) * 1980-11-29 1982-06-07 Tokyo Shibaura Electric Co Hybrid integrated circuit device
JPS57121256A (en) * 1981-01-21 1982-07-28 Hitachi Ltd Ceramic multilayer wiring structure
JPS57181144A (en) * 1981-05-01 1982-11-08 Toshiba Corp Semiconductor device

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5559746A (en) * 1978-10-27 1980-05-06 Hitachi Ltd Semiconductor device and its mounting circuit device
JPS5743452A (en) * 1980-08-28 1982-03-11 Mitsubishi Electric Corp Mounting structure for integrated circuit substrate
JPS5791586A (en) * 1980-11-29 1982-06-07 Tokyo Shibaura Electric Co Hybrid integrated circuit device
JPS57121256A (en) * 1981-01-21 1982-07-28 Hitachi Ltd Ceramic multilayer wiring structure
JPS57181144A (en) * 1981-05-01 1982-11-08 Toshiba Corp Semiconductor device

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2016048728A (en) * 2014-08-27 2016-04-07 株式会社村田製作所 Conductive post and manufacturing method of multilayer substrate using conductive post

Also Published As

Publication number Publication date
JPH0536275Y2 (en) 1993-09-14

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